PVHT
www.vishay.com
Vishay Sfernice
High Stability - Very High Temperature (270 °C)
Thin Film Wraparound Chip Resistors, Sulfur Resistant
FEATURES
• Operating temperature range: -55 °C; +250 °C
• Storage temperature: -55 °C; +270 °C
• Gold terminations (< 1 μm thick)
• 5 sizes available (0402, 0603, 0805, 1206,
2010); other sizes upon request
• Temperature coefficient down to 5 ppm/°C
typical, 10 ppm/°C maximum (-55 °C; +270 °C)
DESIGN SUPPORT TOOLS
Models
Available
click logo to get started
• Tolerance down to 0.05 %
• Load life stability: 0.8 % typical (1 % max.) after 2000 h at
250 °C (ambient) at Pn
• Shelf life stability: 1.5 % typical after 8000 h
• SMD wraparound
• 0.02 % upon request
• TCR remains constant after long term storage at 270 °C
• Sulfur resistant (per ASTM B809-95 humid vapor test)
• Material categorization: for definitions of compliance
please see
www.vishay.com/doc?99912
INTRODUCTION
For applications such as down hole applications, the need
for parts able to withstand very severe conditions
(temperature as high as 250 °C powered or up to 270 °C
un-powered) has led Vishay Sfernice to push out the limit of
the thin film technology.
Designers might read the application note “Power
Dissipation Considerations in High Precision Vishay
Sfernice Thin Film Chip Resistors and Arrays
(P, PRA etc…) (High Temperature Application)”
www.vishay.com/doc?53047
in conjunction with this
datasheet to help them to properly design their board and
get the best performances of the PVHT.
Vishay Sfernice research and development engineers will be
willing to support any customer design considerations.
STANDARD ELECTRICAL SPECIFICATIONS
MODEL
PVHT0402
PVHT0603
PVHT0805
PVHT1206
PVHT2010
SIZE
0402
0603
0805
1206
2010
RESISTANCE
RANGE
39 to 45K
39 to 108K
39 to 240K
39 to 900K
39 to 2.5M
RATED POWER
(1)(2)
P
250 °C
W
0.031
0.062
0.100
0.165
0.2
LIMITING ELEMENT
VOLTAGE
V
50
75
150
200
300
TOLERANCE
±%
0.05, 0.1, 0.5, 1
0.05, 0.1, 0.5, 1
0.05, 0.1, 0.5, 1
0.05, 0.1, 0.5, 1
0.05, 0.1, 0.5, 1
TEMPERATURE
COEFFICIENT
(3)
± ppm/°C
5, 10, 15, 25, 30, 50, 55
5, 10, 15, 25, 30, 50, 55
5, 10, 15, 25, 30, 50, 55
5, 10, 15, 25, 30, 50, 55
5, 10, 15, 25, 30, 50, 55
Notes
(1)
For power handling improvement, please refer to application note 53047 “Power Dissipation Considerations in High Precision Vishay
Sfernice Thin Film Chip Resistors and Arrays (High Temperature Applications)”
www.vishay.com/doc?/53047
and consult Vishay Sfernice
(2)
See derating curve on next page
(3)
See Table 1 on next page
CLIMATIC SPECIFICATIONS
Operating temperature range
Storage temperature range
-55 °C; +250 °C
-55 °C; +270 °C
MECHANICAL SPECIFICATIONS
Substrate
Resistive Element
Passivation
Protection
Terminations
Alumina
Thin Film
Silicon nitride (Si
3
N
4
)
Epoxy + Silicone
Gold (< 1 μm) over nickel barrier
PERFORMANCE VS. HUMID SULFUR VAPOR
Test conditions
Test results
Revision: 04-Jan-2019
50 °C ± 2 °C, 85 % ± 4 % RH,
exposure time 500 h
Resistance drift < (0.05 %
R
+ 0.05
),
no corrosion products observed
Caution:
Performances obtained with following mounting conditions:
• Test board material: alumina
• Solder paste: PbSnAg (93.5/5/1.5)
Document Number: 53060
1
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
PVHT
www.vishay.com
Vishay Sfernice
5 ppm/°C
10 ppm/°C
10 ppm/°C
15 ppm/°C
25 ppm/°C
30 ppm/°C
50 ppm/°C
55 ppm/°C
0 °C; +70 °C
-55 °C; +270 °C
-55 °C; +155 °C
-55 °C; +270 °C
-55 °C; +155 °C
-55 °C; +270 °C
-55 °C; +155 °C
-55 °C; +270 °C
TABLE 1 - TEMPERATURE COEFFICIENT
Z
Y
E
H
TABLE 2
SERIES
0402
0603
0805
1206
2010
RANGE ()
39 to < 50
50 to 45K
39 to < 50
50 to 108K
39 to < 50
50 to 240K
39 to < 50
50 to 900K
39 to < 50
50 to 2.5M
TOL. (± %)
0.1, 0.5, 1
0.05, 0.1, 0.5, 1
0.1, 0.5, 1
0.05, 0.1, 0.5, 1
0.1, 0.5, 1
0.05, 0.1, 0.5, 1
0.1, 0.5, 1
0.05, 0.1, 0.5, 1
0.1, 0.5, 1
0.05, 0.1, 0.5, 1
TCR CODE
Z; Y; E; H
Z; Y; E; H
Z; Y; E; H
Z; Y; E; H
Z; Y; E; H
Z; Y; E; H
Z; Y; E; H
Z; Y; E; H
Z; Y; E; H
Z; Y; E; H
POWER DERATING CURVE
Rated Power (W)
Rated Power (W)
0
50
100
150
200
250
300
0.08
0.25
0.06
0.20
0.15
0.04
0.10
0.02
0.05
0
0
0
50
100
150
200
250
300
Ambient Temperature (°C)
PVHT0402 Power Derating Curve
Ambient Temperature (°C)
PVHT0805 Power Derating Curve
Rated Power (W)
Rated Power (W)
0
50
100
150
200
250
300
0.150
0.125
0.100
0.075
0.050
0.025
0
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0
50
100
150
200
250
300
Ambient Temperature (°C)
PVHT0603 Power Derating Curve
Revision: 04-Jan-2019
Ambient Temperature (°C)
PVHT1206 Power Derating Curve
Document Number: 53060
2
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
PVHT
www.vishay.com
Vishay Sfernice
Rated Power (W)
1.2
1.0
0.8
0.6
0.4
0.2
0
0
50
100
150
200
250
300
Ambient Temperature (°C)
PVHT2010 Power Derating Curve
DIMENSIONS
in millimeters (inches)
A
D
D
C
B
E
E
A
CASE SIZE
MAX. TOL.
+0.152 (+0.006)
MIN. TOL.
-0.152 (-0.006)
NOMINAL
0402
0603
0805
1206
2010
1.00 (0.039)
1.52 (0.060)
1.91 (0.075)
3.06 (0.120)
5.08 (0.200)
B
MAX. TOL.
+0.127 (+0.005)
MIN. TOL.
-0.127 (-0.005)
NOMINAL
0.60 (0.024)
0.85 (0.033)
1.27 (0.050)
1.60 (0.063)
2.54 (0.100)
0.4 (0.016)
± 0.051 (0.002)
C
NOMINAL
0.25 (0.010)
0.38 (0.015)
0.40 (0.016)
0.48 (0.019)
0.13 (0.005)
D/E
TOLERANCE
0.1 (0.004)
SUGGESTED LAND PATTERN (TO IPC-7351A)
G
min.
X
max.
Z
max.
CHIP SIZE
0402
0603
0805
1206
2010
DIMENSIONS (in millimeter)
Z
max.
1.55
2.37
2.76
3.91
5.93
G
min.
0.15
0.35
0.74
1.85
3.71
X
max.
0.73
0.98
1.40
1.73
2.67
Revision: 04-Jan-2019
Document Number: 53060
3
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
PVHT
www.vishay.com
STORAGE CURVE
Drift (ppm)
2000
0
-2000
-4000
-6000
-8000
-10 000
-12 000
-14 000
-16 000
- 18 000
0
2000
4000
6000
8000
10 000
Sample
1
Sample
2
Sample
3
Vishay Sfernice
LOAD LIFE STABILITY CURVES
ΔR/R
(%)
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
200
400
600
800
1000
1200
Sample
1
Sample
2
Sample
3
Time (h)
250 °C Drift (Storage) vs. Time
PVHT2010: 0.2 W/250 °C
Time (h)
Note
• Test performed on samples of 3 different values coming from
different lots.
PACKAGING
ESD packaging available: waffle-pack and plastic tape and
reel (low conductivity). Paper tape available upon request
(for sizes 0402, 0603, 0805 and 1206).
NUMBER OF PIECES PER PACKAGE
SIZE MOQ
0402
0603
0805
1206
2010
200
140
60
100
100
WAFFLE PACK
2" × 2"
TAPE AND REEL
MIN.
MAX.
5000
8 mm
4000
1000
8 mm
TAPE
WIDTH
PACKAGING RULES
Waffle Pack
Can be filled up to maximum quantity indicated in the table
here above, taking into account the minimum order quantity.
When quantity ordered exceeds maximum quantity of a
single waffle pack, the waffle packs are stacked up on the
top of each other and closed by one single cover.
To get “not stacked up” waffle pack in case of ordered
quantity > maximum number of pieces per package:
Please consult Vishay Sfernice for specific ordering
code.
Tape and Reel
See part numbering information to get the quantity desired
by tape.
GLOBAL PART NUMBER INFORMATION
GLOBAL PART NUMBERING: PVHT1206Y1001BGT63
(Limited to 18 digits: If more digits are necessary a codification of some digits might be used)
P
V
H
T
1
2
0
6
Y
1
0
0
1
B
G
T
6
3
GLOBAL
MODEL
PVHT
SIZE
0402
0603
0805
1206
2010
TCR
Z
Y
E
H
VALUE
The first three digits are
significant figures and
the last digit specifies
the number of zeros to
follow, R designates
decimal point
10R0
= 10
3901
= 3900
1004
= 1 M
TOLERANCE
W
= 0.05 %
B
= 0.1 %
D
= 0.5 %
F
=1%
TERMINATION
G
= gold
PACKAGING
1 or 2 digits:
see codification of
packaging table
OPTION
Leave blank
if no option
Revision: 04-Jan-2019
Document Number: 53060
4
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
PVHT
www.vishay.com
Vishay Sfernice
PACKAGING
100 min., 1 mult
100 min., 100 mult (available only in size 1206)
100 min., 1 mult
100 min., 100 mult
250 min., 250 mult
500 min., 500 mult
1000 min., 1000 mult
2500 min., 2500 mult
Full tape (quantity depending on size of chips)
100 min., 1 mult
100 min., 100 mult
250 min., 250 mult
500 min., 500 mult
1000 min., 1000 mult
2500 min., 2500 mult
Full tape (quantity depending on size of chips)
CODIFICATION OF PACKAGING
CODE
WAFFLE PACK
W
WA
PLASTIC TAPE (standard tape for all sizes)
T
TA
TB
TC
TD
TE
TF
PT
PA
PB
PC
PD (not available for size 0402)
PE (not available for size 0402)
PF (not available for size 0402)
PAPER TAPE (Available for 0402, 0603, 0805 and 1206. Please consult Vishay Sfernice for 2010 size.)
Revision: 04-Jan-2019
Document Number: 53060
5
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
DSP 与 ARM 处理器
