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PX-721-EDJ-EABA-647M239400

LVDS Output Clock Oscillator, 647.2394MHz Nom, ROHS COMPLIANT, HERMETIC SEALED PACKAGE-6

器件类别:无源元件    振荡器   

厂商名称:Vectron International, Inc.

厂商官网:http://www.vectron.com/

器件标准:  

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器件参数
参数名称
属性值
是否无铅
不含铅
是否Rohs认证
符合
厂商名称
Vectron International, Inc.
Reach Compliance Code
compli
其他特性
ENABLE/DISABLE FUNCTION; COMPLEMENTARY OUTPUT; TAPE AND REEL
最长下降时间
0.35 ns
频率调整-机械
NO
频率稳定性
20%
JESD-609代码
e4
安装特点
SURFACE MOUNT
标称工作频率
647.2394 MHz
最高工作温度
70 °C
最低工作温度
-20 °C
振荡器类型
LVDS
物理尺寸
7.0mm x 5.0mm x 1.62mm
最长上升时间
0.35 ns
最大供电电压
3.63 V
最小供电电压
2.97 V
标称供电电压
3.3 V
表面贴装
YES
最大对称度
55/45 %
端子面层
Gold (Au) - with Nickel (Ni) barrie
文档预览
PX-721
Single Frequency HPLL XO
PX-721
Descrip on
The PX-721 is a crystal oscillator, XO, based upon Vectron’s HPLL high performance phase locked loop frequency mul plier ASIC, that combines
key digital synthesis techniques with VI’s proven core analog technology blocks. A standard low frequency crystal provides the reference to
the frac onal-n synthesizer so that virtually any frequency between 10MHz and 1200 MHz can be factory programmed allowing quick turn
manufacturing.
Features
Applica ons
Features
• Industry Standard Package, 5.0 x 7.0 x 1.8 mm
• HPLL High Performance PLL ASIC
• Ji er < 500 fs-rms (12 kHz to 20 MHz)
• Output Frequencies from 10 MHz to 1200 MHz
• Spurious Suppression, 70 dBc Typical
• 2.5V or 3.3V Supply Voltage
• LVCMOS, LVPECL or LVDS Output Configura ons
• Output Enable
• Compliant to EC RoHS Direc ve
Applica ons
PLL circuits for clock smoothing and frequency transla on
Descrip on
Standard
• 1-2-4 Gigabit Fibre Channel
• 10 Gigabit Fibre Channel
• 10GbE LAN / WAN
• Synchronous Ethernet
• OC-192
• SONET / SDH
INCITS 352-2002
INCITS 364-2003
IEEE 802.3ae
ITU-T G.8262
ITU-T G.709
GR-253-CORE Issue4
Block Diagram
V
DD
COutput
Output
XTAL
LVCMOS
LVPECL
LVDS
HPLL
OE or NC
OE or NC
Gnd
Figure 1 - Block Diagram
Page 1 of 9
Vectron Interna onal • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • h p://www.vectron.com
Rev2: 14 November 2012
PX-721 Single Frequency HPLL XO
Performance Specifica ons
Electrical Performance
Parameter
Voltage
1
Current
Test Conditions
3.3V Option
2.5V Option
LVCMOS
Symbol
Supply
V
DD
I
DD
Min
2.97
2.25
-
-
-
-40
0.75 x V
DD
-
Typ
3.3
2.5
90
99
120
-
-
-
Max
3.63
2.75
98
108
130
+85
-
0.5
Units
V
LVDS
LVPECL
Operating Temperature
1, 3
Output Enable (OE)
V
IH
V
IL
mA
°C
V
T
OP
Frequency
Nominal Frequency
1
Temperature Stability
1, 6
LVPECL/LVDS
LVCMOS
T
A
= -40 to +85°C
mid-level
swing (diff )
LVDS Output
LVCMOS Output
mid-level
swing (diff )
f
N
f
STAB
Outputs
V
O
V
OD
V
O
V
OD
V
OH
V
OL
10
10
-
-
-
±20
1200
160
-
MHz
ppm
LVPECL Output
V
DD
-1.42
1.1
1.4
300
0.9 x V
DD
-
-
-
45
65
-
-
1.6
450
-
-
-
-
50
70
-
-
V
DD
-1.25
1.9
1.8
600
V
DD
0.1 x V
DD
350
1.2
55
-
1000
500
V
V
PP
V
mV
PP
V
V
ps
ns
%
dBc
fs-rms
fs-rms
Rise/Fall Time (20/80%)
2,5
Symmetry
2,3
LVPECL/LVDS
LVCMOS with C
L
= 15 pF
LVPECL: V
DD
-1.3 V (diff )
LVDS: 1.6 V (diff )
LVCMOS: V
DD
/2
12 kHz to 20 MHz
12 kHz to 20 MHz
t
R/
t
f
SYM
Spurious Suppression
6
Jitter
6
(Performance Option N)
Jitter
6
(Performance Option A)
1]
2]
3]
4]
5]
6]
фJ
фJ
-
-
See Standard Frequencies and Ordering Informa on (Pg 8).
Parameters are tested with produc on test circuit (See Figure 2 for LVCMOS, Figure 3 for LVPECL and Figure 4 for LVDS).
Parameters are tested at ambient temperature with test limits guard-banded for specified opera ng temperature.
Measured as the maximum devia on from the best straight-line fit, per MIL-0-55310.
Parameters are described with waveform diagram below (Figure 5).
Not tested in produc on, guaranteed by design, verified at qualifica on.
Page 2 of 9
Vectron Interna onal • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • h p://www.vectron.com
Rev2: 14 November 2012
PX-721 Single Frequency HPLL XO
Test Circuits & Output Waveform
+3.3V
OE or NC
10nF
1nF
1
6
1
6
10nF
Scope
3
10nF
4
200
200
10k
10k
OE or NC
+3.3V
10nF
1nF
OE or NC
2
5
NC
39
Scope
10nF
OE or NC
2
5
3
4
10k
10nF
VMD
VMD
10nF
Figure 2 - LVCMOS Produc on Test Circuit
Figure 3 - LVPECL Produc on Test Circuit
+3.3V
OE or NC
10nF
1nF
1
6
10nF
Scope
3
10nF
4
10k
10k
t
R
80
%
t
F
OE or NC
2
5
Vs
20
%
On Time
10nF
VMD
Period
Figure 4 - LVDS Produc on Test Circuit
Figure 5 - Waveform Diagram
Absolute Maximum Ratings
Parameter
Power Supply
Input Current
Output Current
Output Enable
Storage Temperature
Soldering Temperature / Duration
Symbol
V
DD
I
IN
I
OUT
OE
T
STR
T
PEAK
/ t
P
Ratings
0 to 3.8
100
25
0 to V
DD
-55 to 125
260 / 40
Unit
V
mA
mA
V
°C
°C / sec
Page 3 of 9
Vectron Interna onal • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • h p://www.vectron.com
Rev2: 14 November 2012
PX-721 Single Frequency HPLL XO
LVPECL Applica on Diagrams
+3.3V
OE or NC
10nF
1nF
1
6
10nF
OE or NC
2
5
10nF
3
4
240
240
3
4
82
82
OE or NC
2
5
10nF
1
6
130
130
10nF
OE or NC
+3.3V
10nF
+3.3V
1nF
Figure 6 - Single Resistor Termina on Scheme
Resistor values are typically 120 to 240 ohms for 3.3V opera on and 82 to 120 ohms for 2.5V
opera on.
Figure 7 - Pull Up Pull Down Termina on
Resistor values are typically for 3.3V opera on
For 2.5V opera on, the resistor to ground is 62 ohms and the resistor to supply is 240 ohms
There are numerous applica on notes on termina ng and interfacing PECL logic and the two most common methods are a single resistor to ground, Figure 6,
and a pull-up/pull-down scheme as shown in Figure 7. An AC coupling capacitor is op onal, depending on the applica on and the input logic requirements of
the next stage.
One of the most important considera ons is termina ng the Output and Complementary Outputs equally. An unused output should not be le un-
terminated, and if one of the two outputs is le open it will result in excessive ji er on both. PC board layout must take this and 50 ohm impedance matching
into account. Load matching and power supply noise are the main contributors to ji er related problems.
LVDS Applica on Diagrams
+3.3V
OE or NC
10nF
1nF
1
6
+3.3V
OE or NC
10nF
1nF
1
6
10nF
OE or NC
2
5
100
3
4
10nF
OE or NC
2
5
Receiver
100
Receiver
3
4
Figure 8 - LVDS to LVDS, internal 100Ω
Some LVDS structures have an internal 100 ohm resistor on the
input and do not need addi onal components.
Figure 9 - LVDS to LVDS, External 100Ω and AC block ing caps
One of the most important considera ons is termina ng the Output and Complementary Outputs equally. An unused output should not be le un-
terminated, and if one of the two outputs is le open it will result in excessive ji er on both. PC board layout must take this and 50 ohm impedance matching
into account. Load matching and power supply noise are the main contributors to ji er related problems.
Page 4 of 9
Vectron Interna onal • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • h p://www.vectron.com
Rev2: 14 November 2012
PX-721 Single Frequency HPLL XO
Typical Characteris cs
Figure 10 - Typical Phase Noise/Ji er Performance - INTEGER Mode
Page 5 of 9
Vectron Interna onal • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • h p://www.vectron.com
Rev2: 14 November 2012
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