PYA28C010
128K x 8 EEPROM
FEATURES
Access Times of 120, 150, 200, and 250ns
Single 5V±10% Power Supply
Simple Byte and Page Write
Low Power CMOS:
- 60 mA Active Current
- 500 µA Standby Current
Fast Write Cycle Times
Software Data Protection
Fully TTL Compatible Inputs and Outputs
Endurance:
- 10,000 Cycles/byte
- 100,000 Cycles/page
Data Retention: 100 Years
Available in the following package:
– 32-Pin 600 mil Ceramic DIP
– 32-Pin Ceramic LCC (450x550 mils)
– 32-Pin Solder Seal Flatpack
– 44-Pin Ceramic LCC (650x650 mils)
DESCRIPTIOn
The PYA28C010 is a 5 Volt 128Kx8 EEPROM using float-
ing gate CMOS Technology. The device supports 64-byte
page write operation. The PYA28C010 features
DATA
and
Toggle Bit Polling as well as a system software scheme
used to indicate early completion of a Write Cycle. The
device also includes user-optional software data protection.
Data Retention is 100 Years. The device is available in
a 32-Pin 600 mil wide Ceramic DIP, 32-Pin LCC, 32-Pin
Solder Seal Flatpack and 44-Pin Ceramic LCC.
FUnCTIOnAL BLOCk DIAgRAM
PIn COnFIgURATIOn
DIP (C10)
LCC (L6)
Document #
EEPROM103
REV 03
Revised July 2014
PYA28C010 - 128K x 8 EEPROM
OPERATIOn
READ
Read operations are initiated by both
OE
and
CE
LOW. The
read operation is terminated by either
CE
or
OE
returning HIGH.
This two line control architecture eliminates bus contention in a
system environment. The data bus will be in a high impedance
state when either
OE
or
CE
is HIGH.
DATA POLLIng
WRITE
Write operations are initiated when both
CE
and
WE
are LOW
and
OE
is HIGH. The PYA28C010 supports both a
CE
and
WE
controlled write cycle. That is, the address is latched by the fall-
ing edge of either
CE
or
WE,
whichever occurs last. Similarly,
the data is latched internally by the rising edge of either
CE
or
WE,
whichever occurs first. A byte write operation, once initi-
ated, will automatically continue to completion, typically within
5 ms.
The PYA28C010 features
DATA
Polling as a method to indicate
to the host system that the byte write or page write cycle has
completed.
DATA
Polling allows a simple bit test operation to
determine the status of the PYA28C010, eliminating additional
interrupts or external hardware. During the internal program-
ming cycle, any attempt to read the last byte written will produce
the complement of that data on I/O
7
(i.e., write data=0xxx xxxx,
read data=1xxx xxxx). Once the programming cycle is com-
plete, I/O
7
will reflect true data. Note: If the PYA28C010 is in
the protected state and an illegal write operation is attempted,
DATA
Polling will not operate.
TOggLE BIT
PAgE WRITE
The page write feature of the AS28C010 allows the entire
memory to be written in 5 seconds. Page write allows two to
two hundred fifty-six bytes of data to be consecutively written
to the PYA28C010 prior to the commencement of the internal
programming cycle. The host can fetch data from another de-
vice within the system during a page write operation (change the
source address), but the page address (A
8
through A
16
) for each
subsequent valid write cycle to the part during this operation
must be the same as the initial page address.
The page write mode can be initiated during any write opera-
tion. Following the initial byte write cycle, the host can write an
additional one to two hundred fifty-six bytes in the same manner
as the first byte was written. Each successive byte load cycle,
started by the
WE
HIGH to LOW transition, must begin within
100µs of the falling edge of the preceding
WE.
If a subsequent
WE
HIGH to LOW transition is not detected within 100µs, the
internal automatic programming cycle will commence. There
is no page write window limitation. Effectively the page write
window is infinitely wide, so long as the host continues to access
the device within the byte load cycle time of 100µs.
The PYA28C010 also provides another method for determining
when the internal write cycle is complete. During the internal
programming cycle, I/O
6
will toggle from HIGH to LOW and LOW
to HIGH on subsequent attempts to read the device. When the
internal cycle is complete the toggling will cease and the device
will be accessible for addtional read or write operations.
DATA PROTECTIOn
Pyramid Semiconductor has incorporated both hardware and
software features that will protect the memory against inadver-
tent writes during transitions of the host system power supply.
HARDWARE PROTECTIOn
Hardware features protect against inadvertent writes to the PY-
A28C010 in the following ways: (a) V
CC
sense - if V
CC
is below
3.8V (typical) the write function is inhibited; (b) V
CC
power-on
delay - once V
CC
has reached 3.8V the device will automatically
time out 5 ms (typical) before allowing a write; (c) write inhibit
- holding any one of
OE
low,
CE
high or
WE
high inhibits write
cycles; (d) noise filter - pulses of less than 15 ns (typical) on the
WE
or
CE
inputs will not initiate a write cycle.
SOFTWARE DATA PROTECTIOn
WRITE
The PYA28C010 provides the user two write operation status
bits. These can be used to optimize a system write cycle time.
The status bits are mapped onto the I/O bus as shown below.
A software controlled data protection feature has been imple-
mented on the PYA28C010. When enabled, the software data
protection (SDP), will prevent inadvertent writes. The SDP fea-
ture may be enabled or disabled by the user; the PYA28C010 is
shipped from Pyramid Semiconductor with SDP disabled.
SDP is enabled by the host system issuing a series of three
write commands; three specific bytes of data are written to three
specific addresses (refer to Software Data Protection Algo-
rithm). After writing the 3-byte command sequence and after
t
WC
the entire PYA28C010 will be protected against inadvertent
write operations. It should be noted, that once protected the
host may still perform a byte or page write to the PYA28C010.
This is done by preceding the data to be written by the same
3-byte command sequence used to enable SDP.
Once set, SDP will remain active unless the disable command
sequence is issued. Power transitions do not disable SDP and
SDP will protect the PYA28C010 during power-up and power-
down conditions. All command sequences must conform to the
page write timing specifications. The data in the enable and
disable command sequences is not written to the device and the
memory addresses used in the sequence may be written with
data in either a byte or page write operation.
After setting SDP, any attempt to write to the device without the
Document #
EEPROM103
REV 03
Page 2
PYA28C010 - 128K x 8 EEPROM
3-byte command sequence will start the internal write timers.
No data will be written to the device; however, for the duration of
tWC, read operations will effectively be polling operations.
DEVICE IDEnTIFICATIOn
An extra 128-bytes of EEPROM memory are available to the
user for device identification. By raising A9 to 12V ± 0.5V and
using address locations 1FF80H to 1FFFFH the bytes may be
written to or read from in the same manner as the regular mem-
ory array.
OPTIOnAL CHIP ERASE MODE
The entire device can be erased using a 6-byte software
code. Please see "Software Chip Erase" application note
at the end of this datasheet for details.
Document #
EEPROM103
REV 03
Page 3
PYA28C010 - 128K x 8 EEPROM
MAxIMUM RATIngS
(1)
Sym
V
CC
V
TERM
T
A
T
BIAS
T
STG
P
T
I
OUT
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND (up to
6.25V)
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
-0.3 to +6.25
-0.5 to +6.25
-55 to +125
-55 to +125
-65 to +150
1.0
50
Unit
V
V
°C
°C
°C
W
mA
RECOMMEnDED OPERATIng COnDITIOnS
grade
(2)
Military
Ambient Temp
-55°C to +125°C
gnD
0V
V
CC
5.0V ± 10%
CAPACITAnCES
(4)
Sym
C
IN
C
OUT
Parameter
(V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz)
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ
10
10
Unit
pF
pF
Input Capacitance
Output Capacitance
DC ELECTRICAL CHARACTERISTICS
Sym Parameter
V
IH
V
IL
V
HC
V
LC
V
OL
V
OH
I
LI
I
LO
I
SB
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Output Low Voltage (TTL Load)
Output High Voltage (TTL Load)
Input Leakage Current
Output Leakage Current
(Over Recommended Operating Temperature & Supply Voltage)
(2)
Test Conditions
PYA28C010
Min
2.0
-0.5
(3)
V
CC
- 0.2
-0.5
(3)
I
OL
= +2.1 mA, V
CC
= Min
I
OH
= -0.4 mA, V
CC
= Min
V
CC
= Max
V
IN
= GND to V
CC
V
CC
= Max,
CE
= V
IH
,
V
OUT
= GND to V
CC
CE
≥ V
IH
,
OE
= V
IL
,
Standby Power Supply Current (TTL Input Levels)
V
CC
= Max,
f = Max, Outputs Open
CE
≥ V
HC
,
I
SB1
Standby Power Supply Current (CMOS Input Levels)
V
CC
= Max,
f = Max, Outputs Open,
V
IN
≤ V
LC
or V
IN
≥ V
HC
CE
=
OE
= V
IL
,
I
CC
Supply Current
WE
= V
IH
,
All I/O's = Open,
Inputs = V
CC
= 5.5V
notes:
1. Stresses greater than those listed under
MAxIMuM RATINGS
may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAxIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than -3.0V and -100mA,
respectively, are permissible for pulse widths up to 20ns.
4. This parameter is sampled and not 100% tested.
—
—
—
Max
V
CC
+ 0.3
0.8
V
CC
+ 0.5
0.2
0.45
Unit
V
V
V
V
V
V
2.4
-10
-10
+10
+10
µA
µA
3
mA
300
µA
60
µA
Document #
EEPROM103
REV 03
Page 4
PYA28C010 - 128K x 8 EEPROM
POWER-UP TIMIng
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read operation
Power-up to Write operation
Max
100
5
Unit
µs
ms
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym
t
AVAV
t
AVQV
t
ELQV
t
OLQV
t
ELQx
t
EHQZ
t
OLQx
t
OHQZ
t
AVQx
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Chip Disable to to Output in High Z
Output Enable to Output in Low Z
Output Disable to Output in High Z
Output Hold from Address Change
0
0
50
0
0
50
0
50
0
-120
Min
120
120
120
50
0
50
0
50
0
Max
Min
150
150
150
50
0
50
0
50
-150
Max
Min
200
200
200
50
0
50
-200
Max
Min
250
250
250
50
-250
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMIng WAVEFORM OF READ CYCLE
Document #
EEPROM103
REV 03
Page 5
