INTEGRATED CIRCUITS
PZ3064
64 macrocell CPLD
Product specification
IC27 Data Handbook
1997 Mar 05
Philips
Semiconductors
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
FEATURES
•
Industry’s first TotalCMOS™ PLD – both CMOS design and
•
Fast Zero Power (FZP™) design technique provides ultra-low
power and very high speed
process technologies
DESCRIPTION
The PZ3064 CPLD (Complex Programmable Logic Device) is the
second in a family of Fast Zero Power (FZP™) CPLDs from Philips
Semiconductors. These devices combine high speed and zero
power in a 64 macrocell CPLD. With the FZP™ design technique,
the PZ3064 offers true pin-to-pin speeds of 10ns, while
simultaneously delivering power that is less than 50µA at standby
without the need for ‘turbo bits’ or other power down schemes. By
replacing conventional sense amplifier methods for implementing
product terms (a technique that has been used in PLDs since the
bipolar era) with a cascaded chain of pure CMOS gates, the
dynamic power is also substantially lower than any competing CPLD
– 70% lower at 50MHz. These devices are the first TotalCMOS™
PLDs, as they use both a CMOS process technology
and
the
patented full CMOS FZP™ design technique. For 5V applications,
Philips also offers the high speed PZ5064 CPLD that offers these
features in a full 5V implementation.
The Philips FZP™ CPLDs introduce the new patent-pending XPLA™
(eXtended Programmable Logic Array) architecture. The XPLA™
architecture combines the best features of both PLA and PAL™ type
structures to deliver high speed and flexible logic allocation that
results in superior ability to make design changes with fixed pinouts.
The XPLA™ structure in each logic block provides a fast 10ns PAL™
path with 5 dedicated product terms per output. This PAL™ path is
joined by an additional PLA structure that deploys a pool of 32
product terms to a fully programmable OR array that can allocate
the PLA product terms to any output in the logic block. This
combination allows logic to be allocated efficiently throughout the
logic block and supports as many as 37 product terms on an output.
The speed with which logic is allocated from the PLA array to an
output is only 2.5ns, regardless of the number of PLA product terms
used, which results in worst case t
PD
’s of only 12.5ns from any pin
to any other pin. In addition, logic that is common to multiple outputs
can be placed on a single PLA product term and shared across
multiple outputs via the OR array, effectively increasing design
density.
The PZ3064 CPLDs are supported by industry standard CAE tools
(Cadence, Mentor, Synopsys, Synario, Viewlogic, MINC), using text
(Abel, VHDL, Verilog) and/or schematic entry. Design verification
uses industry standard simulators for functional and timing
simulation. Development is supported on personal computer, Sparc,
and HP platforms. Device fitting uses either Minc or Philips
Semiconductors-developed tools.
The PZ3064 CPLD is reprogrammable using industry standard
device programmers from vendors such as Data I/O, BP
Microsystems, SMS, and others.
•
High speed pin-to-pin delays of 10ns
•
Ultra-low static power of less than 50µA
•
Dynamic power that is 70% lower at 50MHz than competing
•
100% routable with 100% utilization while all pins and all
macrocells are fixed
devices
•
Deterministic timing model that is extremely simple to use
•
4 clocks with programmable polarity at every macrocell
•
Support for complex asynchronous clocking
•
Innovative XPLA™ architecture combines high speed with
•
1000 erase/program cycles guaranteed
•
20 years data retention guaranteed
•
Logic expandable to 37 product terms
•
PCI compliant
•
Advanced 0.5µ E
2
CMOS process
•
Security bit prevents unauthorized access
•
Design entry and verification using industry standard and Philips
•
Reprogrammable using industry standard device programmers
•
Innovative Control Term structure provides either sum terms or
product terms in each logic block for:
–
Programmable 3-State buffer
–
Asynchronous macrocell register preset/reset
CAE tools
extreme flexibility
•
Programmable global 3-State pin facilitates ‘bed of nails’ testing
•
Available in PLCC, TQFP, and PQFP packages
•
Available in both Commercial and Industrial grades
Table 1. PZ3064 Features
PZ3064
Usable gates
Maximum inputs
Maximum I/Os
Number of macrocells
Propagation delay (ns)
Packages
2000
68
64
64
10
44-pin PLCC, 44-pin TQFP,
68-pin PLCC, 84-pin PLCC,
100-pin PQFP
without using logic resources
PAL is a registered trademark of Advanced Micro Devices, Inc.
1997 Mar 05
82
853–1891 17824
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
ORDERING INFORMATION
ORDER CODE
PZ3064-10A44
PZ3064-12A44
PZ3064I12A44
PZ3064I15A44
PZ3064-10BC
PZ3064-12BC
PZ3064I12BC
PZ3064I15BC
PZ3064-10A68
PZ3064-12A68
PZ3064I12A68
PZ3064I15A68
PZ3064-10A84
PZ3064-12A84
PZ3064I12A84
PZ3064I15A84
PZ3064-10BB1
PZ3064-12BB1
PZ3064I12BB1
PZ3064I15BB1
DESCRIPTION
44-pin PLCC, 10ns t
PD
44-pin PLCC, 12ns t
PD
44-pin PLCC, 12ns t
PD
44-pin PLCC, 15ns t
PD
44-pin TQFP, 10ns t
PD
44-pin TQFP, 12ns t
PD
44-pin TQFP, 12ns t
PD
44-pin TQFP, 15ns t
PD
68-pin PLCC, 10ns t
PD
68-pin PLCC, 12ns t
PD
68-pin PLCC, 12ns t
PD
68-pin PLCC, 15ns t
PD
84-pin PLCC, 10ns t
PD
84-pin PLCC, 12ns t
PD
84-pin PLCC, 12ns t
PD
84-pin PLCC, 15ns t
PD
100-pin PQFP, 10ns t
PD
100-pin PQFP, 12ns t
PD
100-pin PQFP, 12ns t
PD
100-pin PQFP, 15ns t
PD
DESCRIPTION
Commercial temp range, 3.3 volt power supply,
±
10%
Commercial temp range, 3.3 volt power supply,
±
10%
Industrial temp range, 3.3 volt power supply,
±
10%
Industrial temp range, 3.3 volt power supply,
±
10%
Commercial temp range, 3.3 volt power supply,
±
10%
Commercial temp range, 3.3 volt power supply,
±
10%
Industrial temp range, 3.3 volt power supply,
±
10%
Industrial temp range, 3.3 volt power supply,
±
10%
Commercial temp range, 3.3 volt power supply,
±
10%
Commercial temp range, 3.3 volt power supply,
±
10%
Industrial temp range, 3.3 volt power supply,
±
10%
Industrial temp range, 3.3 volt power supply,
±
10%
Commercial temp range, 3.3 volt power supply,
±
10%
Commercial temp range, 3.3 volt power supply,
±
10%
Industrial temp range, 3.3 volt power supply,
±
10%
Industrial temp range, 3.3 volt power supply,
±
10%
Commercial temp range, 3.3 volt power supply,
±
10%
Commercial temp range, 3.3 volt power supply,
±
10%
Industrial temp range, 3.3 volt power supply,
±
10%
Industrial temp range, 3.3 volt power supply,
±
10%
DRAWING NUMBER
SOT187-2
SOT187-2
SOT187-2
SOT187-2
SOT376-1
SOT376-1
SOT376-1
SOT376-1
SOT188-3
SOT188-3
SOT188-3
SOT188-3
SOT189-3
SOT189-3
SOT189-3
SOT189-3
SOT382-1
SOT382-1
SOT382-1
SOT382-1
XPLA™ ARCHITECTURE
Figure 1 shows a high level block diagram of a 64 macrocell device
implementing the XPLA™ architecture. The XPLA™ architecture
consists of logic blocks that are interconnected by a Zero-power
Interconnect Array (ZIA). The ZIA is a virtual crosspoint switch. Each
logic block is essentially a 36V16 device with 36 inputs from the ZIA
and 16 macrocells. Each logic block also provides 32 ZIA feedback
paths from the macrocells and I/O pins.
From this point of view, this architecture looks like many other CPLD
architectures. What makes the CoolRunner™ family unique is what
is inside each logic block and the design technique used to
implement these logic blocks. The contents of the logic block will be
described next.
Logic Block Architecture
Figure 2 illustrates the logic block architecture. Each logic block
contains control terms, a PAL array, a PLA array, and 16 macrocells.
the 6 control terms can individually be configured as either SUM or
PRODUCT terms, and are used to control the preset/reset and
output enables of the 16 macrocells’ flip-flops. The PAL array
consists of a programmable AND array with a fixed OR array, while
the PLA array consists of a programmable AND array with a
programmable OR array. The PAL array provides a high speed path
through the array, while the PLA array provides increased product
term density.
Each macrocell has 5 dedicated product terms from the PAL array.
The pin-to-pin t
PD
of the PZ3064 device through the PAL array is
10ns. If a macrocell needs more than 5 product terms, it simply gets
the additional product terms from the PLA array. The PLA array
consists of 32 product terms, which are available for use by all 16
macrocells. The additional propagation delay incurred by a
macrocell using 1 or all 32 PLA product terms is just 2.5ns. So the
total pin-to-pin t
PD
for the PZ3064 using 6 to 37 product terms is
12.5ns (10ns for the PAL + 2.5ns for the PLA).
1997 Mar 05
83
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
MC0
MC1
I/O
MC15
16
16
ZIA
MC0
MC1
I/O
MC15
16
16
16
16
LOGIC
BLOCK
36
36
LOGIC
BLOCK
16
16
LOGIC
BLOCK
36
36
LOGIC
BLOCK
MC0
MC1
I/O
MC15
MC0
MC1
I/O
MC15
SP00439
Figure 1. Philips XPLA CPLD Architecture
36 ZIA INPUTS
CONTROL
6
5
PAL
ARRAY
PLA
ARRAY
(32)
TO 16 MACROCELLS
SP00435
Figure 2. Philips Logic Block Architecture
1997 Mar 05
84
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
Macrocell Architecture
Figure 3 shows the architecture of the macrocell used in the
CoolRunner™ family. The macrocell consists of a flip-flop that can be
configured as either a D or T type. A D-type flip-flop is generally
more useful for implementing state machines and data buffering. A
T-type flip-flop is generally more useful in implementing counters. All
CoolRunner™ family members provide both synchronous and
asynchronous clocking and provide the ability to clock off either the
falling or rising edges of these clocks. These devices are designed
such that the skew between the rising and falling edges of a clock
are minimized for clocking integrity. There are 4 clocks available on
the PZ3064 device. Clock 0 (CLK0) is designated as the
“synchronous” clock and must be driven by an external source.
Clock 1 (CLK1), Clock 2 (CLK2), and Clock 3 (CLK3) can either be
used as a synchronous clock (driven by an external source) or as an
asynchronous clock (driven by a macrocell equation).
Two of the control terms (CT0 and CT1) are used to control the
Preset/Reset of the macrocell’s flip-flop. The Preset/Reset feature
for each macrocell can also be disabled. Note that the Power-on
Reset leaves all macrocells in the “zero” state when power is
properly applied. The other 4 control terms (CT2–CT5) can be used
to control the Output Enable of the macrocell’s output buffers. The
reason there are as many control terms dedicated for the Output
Enable of the macrocell is to insure that all CoolRunner™ devices
are PCI compliant. The macrocell’s output buffers can also be
always enabled or disabled. All CoolRunner™ devices also provide a
Global Tri-State (GTS) pin, which, when pulled Low, will 3-State all
the outputs of the device. This pin is provided to support “In-Circuit
Testing” or “Bed-of-Nails Testing”.
There are two feedback paths to the ZIA: one from the macrocell,
and one from the I/O pin. The ZIA feedback path before the output
buffer is the macrocell feedback path, while the ZIA feedback path
after the output buffer is the I/O pin ZIA path. When the macrocell is
used as an output, the output buffer is enabled, and the macrocell
feedback path can be used to feedback the logic implemented in the
macrocell. When the I/O pin is used as an input, the output buffer
will be 3-Stated and the input signal will be fed into the ZIA via the
I/O feedback path, and the logic implemented in the buried
macrocell can be fed back to the ZIA via the macrocell feedback
path. It should be noted that unused inputs or I/Os should be
properly terminated.
TO ZIA
D/T
INIT
(P or R)
CLK0
CLK0
CLK1
CLK1
CLK2
CLK2
CLK3
CLK3
Q
GTS
GND
CT0
CT1
GND
CT2
CT3
CT4
CT5
V
CC
GND
SP00457
Figure 3. PZ3064 Macrocell Architecture
1997 Mar 05
85
