INTEGRATED CIRCUITS
PZ5128
128 macrocell CPLD
Product specification
Supersedes data of 1997 Aug 12
IC27 Data Handbook
1998 Jul 23
Philips
Semiconductors
Philips Semiconductors
Product specification
128 macrocell CPLD
PZ5128
FEATURES
•
Industry’s first TotalCMOS™ PLD – both CMOS design and
•
Fast Zero Power (FZP™) design technique provides ultra-low
•
IEEE 1149.1–compliant, JTAG Testing Capability
–
4 pin JTAG interface (TCK, TMS, TDI, TDO)
–
IEEE 1149.1 TAP Controller
–
JTAG commands include: Bypass, Sample/Preload, Extest,
Usercode, Idcode, HighZ
power and very high speed
process technologies
Table 1. PZ5128 Features
PZ5128
Usable gates
Maximum inputs
Maximum I/Os
Number of macrocells
Propagation delay (ns)
Packages
4000
100
96
128
7.5
84-pin PLCC, 100-pin PQFP,
100-pin TQFP 128-pin LQFP,
160-pin PQFP
•
5 Volt, In–System Programmable (ISP) using the JTAG interface
–
On–chip supervoltage generation
–
ISP commands include: Enable, Erase, Program, Verify
–
Supported by multiple ISP programming platforms
DESCRIPTION
The PZ5128 CPLD (Complex Programmable Logic Device) is the
third in a family of Fast Zero Power (FZP™) CPLDs from Philips
Semiconductors. These devices combine high speed and zero
power in a 128 macrocell CPLD. With the FZP™ design technique,
the PZ5128 offers true pin-to-pin speeds of 7.5ns, while
simultaneously delivering power that is less than 100µA at standby
without the need for ‘turbo bits’ or other power down schemes. By
replacing conventional sense amplifier methods for implementing
product terms (a technique that has been used in PLDs since the
bipolar era) with a cascaded chain of pure CMOS gates, the
dynamic power is also substantially lower than any competing CPLD
– 70% lower at 50MHz. These devices are the first TotalCMOS™
PLDs, as they use both a CMOS process technology
and
the
patented full CMOS FZP™ design technique. For 3V applications,
Philips also offers the high speed PZ3128 CPLD that offers these
features in a full 3V implementation.
The Philips FZP™ CPLDs introduce the new patent-pending XPLA™
(eXtended Programmable Logic Array) architecture. The XPLA™
architecture combines the best features of both PLA and PAL™ type
structures to deliver high speed and flexible logic allocation that
results in superior ability to make design changes with fixed pinouts.
The XPLA™ structure in each logic block provides a fast 10ns PAL™
path with 5 dedicated product terms per output. This PAL™ path is
joined by an additional PLA structure that deploys a pool of 32
product terms to a fully programmable OR array that can allocate
the PLA product terms to any output in the logic block. This
combination allows logic to be allocated efficiently throughout the
logic block and supports as many as 37 product terms on an output.
The speed with which logic is allocated from the PLA array to an
output is only 2ns, regardless of the number of PLA product terms
used, which results in worst case t
PD
’s of only 9.5ns from any pin to
any other pin. In addition, logic that is common to multiple outputs
can be placed on a single PLA product term and shared across
multiple outputs via the OR array, effectively increasing design
density.
The PZ5128 CPLDs are supported by industry standard CAE tools
(Cadence, Exemplar Logic, Minc, Mentor, Synopsys, Synario,
Viewlogic, MINC), using text (Abel, VHDL, Verilog) and/or schematic
entry. Design verification uses industry standard simulators for
functional and timing simulation. Development is supported on
personal computer, Sparc, and HP platforms. Device fitting uses
either MINC or Philips Semiconductors-developed tools.
The PZ5128 CPLD is electrically reprogrammable using industry
standard device programmers from vendors such as Data I/O, BP
Microsystems, SMS, and others. The PZ5128 also includes an
industry-standard, IEEE 1149.1, JTAG interface through which
in-system programming (ISP) and reprogramming of the device is
supported.
•
High speed pin-to-pin delays of 7.5ns
•
Ultra-low static power of less than 100µA
•
Dynamic power that is 70% lower at 50MHz than competing
•
100% routable with 100% utilization while all pins and all
•
Deterministic timing model that is extremely simple to use
•
4 clocks with programmable polarity at every macrocell
•
Support for asynchronous clocking
•
Innovative XPLA™ architecture combines high speed with
•
1000 erase/program cycles guaranteed
•
20 years data retention guaranteed
•
Logic expandable to 37 product terms
•
PCI compliant
•
Advanced 0.5µ E
2
CMOS process
•
Security bit prevents unauthorized access
•
Design entry and verification using industry standard and Philips
•
Reprogrammable using industry standard device programmers
•
Innovative Control Term structure provides either sum terms or
product terms in each logic block for:
–
Programmable 3-State buffer
–
Asynchronous macrocell register preset/reset
CAE tools
extreme flexibility
macrocells are fixed
devices
•
Programmable global 3-State pin facilitates ‘bed of nails’ testing
•
Available in PLCC, TQFP, and PQFP packages
•
Available in both Commercial and Industrial grades
without using logic resources
PAL is a registered trademark of Advanced Micro Devices, Inc.
1998 Jul 23
2
853–2023 19775
Philips Semiconductors
Product specification
128 macrocell CPLD
PZ5128
ORDERING INFORMATION
ORDER CODE
PZ5128–S7A84
PZ5128-S10A84
PZ5128-S12A84
PZ528IS10A84
PZ5128IS15A84
PZ5128–S7BB1
PZ5128-S10BB1
PZ5128-S12BB1
PZ5128IS10BB1
PZ5128IS15BB1
PZ5128–S7BBP
PZ5128-S10BP
PZ5128-S12BP
PZ5128IS10BP
PZ5128IS15BP
PZ5128–S7BE
PZ5128-S10BE
PZ5128-S12BE
PZ5128IS10BE
PZ5128IS15BE
PZ5128–S7BB2
PZ5128-S10BB2
PZ5128-S12BB2
PZ5128IS10BB2
PZ5128IS15BB2
DESCRIPTION
84–pin PLCC, 7.5ns t
PD
84-pin PLCC, 10ns t
PD
84-pin PLCC, 12ns t
PD
84–pin PLCC, 10ns t
PD
84-pin PLCC, 15ns t
PD
100–pin PQFP, 7.5ns t
PD
100-pin PQFP, 10ns t
PD
100-pin PQFP, 12ns t
PD
100–pin PQFP, 10ns t
PD
100-pin PQFP, 15ns t
PD
100–pin TQFP, 7.5ns t
PD
100-pin TQFP, 10ns t
PD
100-pin TQFP, 12ns t
PD
100–pin TQFP, 10ns t
PD
100-pin TQFP, 15ns t
PD
128–LQFP, 7.5ns t
PD
128-pin LQFP, 10ns t
PD
128-pin LQFP, 12ns t
PD
128–pin LQFP, 10ns t
PD
128-pin LQFP, 15ns t
PD
160–pin PQFP, 7.5ns t
PD
160-pin PQFP, 10ns t
PD
160-pin PQFP, 12ns t
PD
160–pin PQFP, 10ns t
PD
160-pin PQFP, 15ns t
PD
DESCRIPTION
Commercial temp range, 5 volt power supply,
±
5%
Commercial temp range, 5 volt power supply,
±
5%
Commercial temp range, 5 volt power supply,
±
5%
Industrial temp range, 5 volt power supply,
±
10%
Industrial temp range, 5 volt power supply,
±
10%
Commercial temp range, 5 volt power supply,
±
5%
Commercial temp range, 5 volt power supply,
±
5%
Commercial temp range, 5 volt power supply,
±
5%
Industrial temprange, 5 volt power supply,
±
10%
Industrial temp range, 5 volt power supply,
±
10%
Commercial temp range, 5 volt power supply,
±
5%
Commercial temp range, 5 volt power supply,
±
5%
Commercial temp range, 5 volt power supply,
±
5%
Industrial temp range, 5 volt power supply,
±
10%
Industrial temp range, 5 volt power supply,
±
10%
Commercial temp range, 5 volt power supply,
±
5%
Commercial temp range, 5 volt power supply,
±
5%
Commercial temp range, 5 volt power supply,
±
5%
Industrial temp range, 5 volt power supply,
±
10%
Industrial temp range, 5 volt power supply,
±
10%
Commercial temp range, 5 volt power supply,
±
5%
Commercial temp range, 5 volt power supply,
±
5%
Commercial temp range, 5 volt power supply,
±
5%
Industrial temp range, 5 volt poweer supply,
±
10%
Industrial temp range, 5 volt power supply,
±
10%
DRAWING NUMBER
SOT189–3
SOT189-3
SOT189-3
SOT189–3
SOT189-3
SOT382–1
SOT382-1
SOT382-1
SOT382–1
SOT382-1
SOT386–1
SOT386-1
SOT386-1
SOT386–1
SOT386-1
SOT425–1
SOT425-1
SOT425-1
SOT425–1
SOT425-1
SOT322–2
SOT322-2
SOT322-2
SOT322–2
SOT322-2
1998 Jul 23
3
Philips Semiconductors
Product specification
128 macrocell CPLD
PZ5128
XPLA™ ARCHITECTURE
Figure 1 shows a high level block diagram of a 128 macrocell device
implementing the XPLA™ architecture. The XPLA™ architecture
consists of logic blocks that are interconnected by a Zero-power
Interconnect Array (ZIA). The ZIA is a virtual crosspoint switch. Each
logic block is essentially a 36V16 device with 36 inputs from the ZIA
and 16 macrocells. Each logic block also provides 32 ZIA feedback
paths from the macrocells and I/O pins.
From this point of view, this architecture looks like many other CPLD
architectures. What makes the CoolRunner™ family unique is what
is inside each logic block and the design technique used to
implement these logic blocks. The contents of the logic block will be
described next.
MC0
MC1
I/O
MC15
16
16
16
16
LOGIC
BLOCK
36
36
LOGIC
BLOCK
MC0
MC1
I/O
MC15
MC0
MC1
I/O
MC15
16
16
ZIA
LOGIC
BLOCK
36
36
LOGIC
BLOCK
16
16
LOGIC
BLOCK
36
36
LOGIC
BLOCK
MC0
MC1
I/O
MC15
MC0
MC1
I/O
MC15
16
16
MC0
MC1
I/O
MC15
16
16
MC0
MC1
I/O
MC15
16
16
16
16
LOGIC
BLOCK
36
36
LOGIC
BLOCK
MC0
MC1
I/O
MC15
SP00464
Figure 1. Philips XPLA CPLD Architecture
1998 Jul 23
4
Philips Semiconductors
Product specification
128 macrocell CPLD
PZ5128
Logic Block Architecture
Figure 2 illustrates the logic block architecture. Each logic block
contains control terms, a PAL array, a PLA array, and 16 macrocells.
the 6 control terms can individually be configured as either SUM or
PRODUCT terms, and are used to control the preset/reset and
output enables of the 16 macrocells’ flip-flops. The PAL array
consists of a programmable AND array with a fixed OR array, while
the PLA array consists of a programmable AND array with a
programmable OR array. The PAL array provides a high speed path
through the array, while the PLA array provides increased product
term density.
Each macrocell has 5 dedicated product terms from the PAL array.
The pin-to-pin t
PD
of the PZ5128 device through the PAL array is
7.5ns. If a macrocell needs more than 5 product terms, it simply gets
the additional product terms from the PLA array. The PLA array
consists of 32 product terms, which are available for use by all 16
macrocells. The additional propagation delay incurred by a
macrocell using 1 or all 32 PLA product terms is just 2ns. So the
total pin-to-pin t
PD
for the PZ5128 using 6 to 37 product terms is
9.5ns (7.5ns for the PAL + 2ns for the PLA).
36 ZIA INPUTS
CONTROL
5
6
PAL
ARRAY
PLA
ARRAY
(32)
SP00435A
Figure 2. Philips XPLA Logic Block Architecture
1998 Jul 23
5
TO 16 MACROCELLS
