Intel
®
7300 Chipset Memory
Controller Hub (MCH)
Datasheet
September 2007
Document Number: 318082-001
Notice:
This document contains preliminary information on new products in production. The specifications are subject to change without notice. Ver-
ify with your local Intel sales office that you have the latest datasheet before finalizing a design
The Intel
®
7300 Chipset Memory Controller Hub (MCH) may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are available on request.
64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device
drivers and applications enabled for Intel® 64 architecture. Performance will vary depending on your hardware and software
configurations. Consult with your system vendor for more information.
Intel® Active Management Technology requires the platform to have an Intel® AMT-enabled chipset, network hardware and
software, as well as connection with a power source and a corporate network connection. With regard to notebooks, Intel AMT
may not be available or certain capabilities may be limited over a host OS-based VPN or when connecting wirelessly, on battery
power, sleeping, hibernating or powered off. For more information, see http://www.intel.com/technology/iamt.
I
2
C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I
2
C bus/protocol and was developed
by Intel. Implementations of the I
2
C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and
North American Philips Corporation.
Intel, Xeon, Pentium, Intel Core, Intel XScale, Intel 6700PXH 64-bit PCI Hub, Intel 6702PXH 64-bit PCI Hub, Intel 64, Intel I/O
Acceleration Technology (Intel I/OAT), Intel 631xESB/632xESB I/O Controller Hub, Intel IOP 348 I/O Processor, 82575 Gigabit
Ethernet controller, Intel Active Management Technology (Intel AMT), Intel QuickData Technology, and the Intel logo are
trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other brands and names are the property of their respective owners.
Copyright © 2006-2007, Intel Corporation.
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Intel
®
7300 Chipset Memory Controller Hub (MCH) Datasheet
Contents
1
Intel
®
7300 Chipset Introduction .................................................................................. 15
1.1
BIOS Selftest Utility ........................................................................................... 15
1.2
Reference Documentation................................................................................... 15
1.2.1 Intel® IOP 348 I/O Processor (Sunrise Lake) Related Documents ................. 17
1.3
Conventions and Terminology ............................................................................. 18
1.3.1 Terminology .......................................................................................... 18
System Overview ....................................................................................................... 27
2.1
Processor Features ............................................................................................ 27
2.2
Intel
®
7300 Chipset MCH Features ...................................................................... 28
2.2.1 Front Side Bus ....................................................................................... 28
2.2.2 System Memory Interface ....................................................................... 28
2.2.3 PCI Express Interfaces ............................................................................ 30
2.2.4 SMBus Interfaces ................................................................................... 30
2.2.5 MCH Bandwidth Summary ....................................................................... 30
2.3
Intel® 631xESB/632xESB I/O Controller Hub Features ........................................... 31
2.4
Additional Platform Components .......................................................................... 32
2.4.1 Intel® 6700PXH/6702PXH 64-bit PCI Hub System Features ......................... 32
2.4.2 Intel® IOP 348 I/O Processor (Sunrise Lake)
Storage I/O Processor Features ................................................................ 33
2.4.3 82563EB/82564EB (Gilgal) Dual-Port 10/100/1000BASE-T PHY .................... 34
2.4.4 82575 (Zoar) Dual Port 10/100/1000 Gigabit Ethernet Controller.................. 35
2.5
System Configuration ........................................................................................ 36
Signal Description....................................................................................................... 37
3.1
Processor Front Side Bus Signals ......................................................................... 38
3.1.1 Processor Front Side Bus 0 ...................................................................... 38
3.1.2 Processor Front Side Bus 1 ...................................................................... 40
3.1.3 Processor Front Side Bus 2 ...................................................................... 42
3.1.4 Processor Front Side Bus 3 ...................................................................... 44
3.2
Fully Buffered DIMM Memory Channels................................................................. 46
3.2.1 FB-DIMM Branch 0 ................................................................................. 46
3.2.2 FB-DIMM Branch 1 ................................................................................. 47
3.3
PCI Express* Signal List ..................................................................................... 48
3.3.1 PCI Express Common Signals................................................................... 48
3.3.2 PCI Express Port 0, Enterprise South Bridge Interface (ESI) ......................... 48
3.3.3 PCI Express Port 1.................................................................................. 48
3.3.4 PCI Express Port 2.................................................................................. 48
3.3.5 PCI Express Port 3.................................................................................. 49
3.3.6 PCI Express Port 4.................................................................................. 49
3.3.7 PCI Express Port 5.................................................................................. 49
3.3.8 PCI Express Port 6.................................................................................. 49
3.3.9 PCI Express Port 7.................................................................................. 50
3.4
System Management Bus Interfaces .................................................................... 50
3.5
XDP Port Signal List ........................................................................................... 51
3.6
JTAG Bus Signal List .......................................................................................... 51
3.7
Clocks, Reset and Miscellaneous .......................................................................... 51
3.8
Power and Ground Signals .................................................................................. 52
Register Description.................................................................................................... 53
4.1
Register Terminology ......................................................................................... 53
4.2
Platform Configuration Structure ......................................................................... 55
4.3
Routing Configuration Accesses ........................................................................... 58
4.3.1 Standard PCI Bus Configuration Mechanism ............................................... 58
3
2
3
4
Intel
®
7300 Chipset Memory Controller Hub (MCH) Datasheet
4.4
4.5
4.6
4.7
4.8
4.3.2 PCI Bus 0 Configuration Mechanism ..........................................................58
4.3.3 Primary PCI and Downstream Configuration Mechanism ...............................59
Device Mapping .................................................................................................59
4.4.1 Special Device and Function Routing .........................................................60
I/O Mapped Registers.........................................................................................62
4.5.1 CFGADR: Configuration Address Register ...................................................62
4.5.2 CFGDAT: Configuration Data Register ........................................................63
MCH Fixed Memory Mapped Registers...................................................................63
Detailed Configuration Space Maps.......................................................................64
Register Definitions ............................................................................................90
4.8.1 PCI Standard Registers............................................................................90
4.8.2 Revision ID (RID): Background .................................................................90
4.8.3 Address Mapping Registers ......................................................................95
4.8.4 AMB Memory Mapped Registers .............................................................. 102
4.8.5 Interrupt Redirection Registers ............................................................... 106
4.8.6 Boot and Reset Registers ....................................................................... 107
4.8.7 Control and Interrupt Registers .............................................................. 111
4.8.8 Snoop Filter Control and Configuration..................................................... 118
4.8.9 PCI Express Device Configuration Registers .............................................. 119
4.8.10 PCI Express Header .............................................................................. 122
4.8.11 PCI Express Power Management Capability Structure................................. 143
4.8.12 PCI Express Message Signalled Interrupts (MSI) Capability Structure ........... 145
4.8.13 PCI Express Capability Structure ............................................................. 150
4.8.14 PCI Express Advanced Error Reporting Capability ...................................... 175
4.8.15 PCI Express IBIST Registers ................................................................... 191
4.8.16 Error Registers ..................................................................................... 197
4.8.17 Debug and Error Injection Registers ........................................................ 213
4.8.18 Memory Control Registers ...................................................................... 221
4.8.19 Memory Ratio Registers ......................................................................... 232
4.8.20 Memory Map Registers .......................................................................... 233
4.8.21 FBD Error Registers............................................................................... 235
4.8.22 FBD Error Log Registers......................................................................... 243
4.8.23 FBD Branch Registers ............................................................................ 249
4.8.24 FBD RAS Registers ................................................................................ 257
4.8.25 FB-DIMM IBIST Registers....................................................................... 263
4.8.26 Serial Presence Detect Registers ............................................................. 269
4.8.27 DMA Engine Configuration Registers ........................................................ 271
5
6
Ball Assignment ........................................................................................................ 285
5.1
Intel
®
7300 Chipset MCH Ball Assignment........................................................... 285
System Address Map ................................................................................................. 335
6.1
Memory Map ................................................................................................... 335
6.1.1 Compatibility Region ............................................................................. 336
6.1.2 Low/Medium Memory ............................................................................ 338
6.1.3 High Extended Memory.......................................................................... 344
6.1.4 Main Memory Region ............................................................................. 344
6.2
Memory Address Disposition.............................................................................. 346
6.2.1 Registers Used for Address Routing ......................................................... 346
6.2.2 Address Disposition for Processor............................................................ 346
6.2.3 Inbound Transactions ............................................................................ 350
6.3
I/O Address Map.............................................................................................. 352
6.3.1 Special I/O addresses............................................................................ 352
6.3.2 Outbound I/O Access ............................................................................ 352
6.3.3 Inbound I/O Access............................................................................... 354
6.4
Configuration Space ......................................................................................... 354
Functional Description ............................................................................................... 355
Intel
®
7300 Chipset Memory Controller Hub (MCH) Datasheet
7
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Processor Front Side Bus .................................................................................. 355
7.1.1 Front Side Bus Overview ....................................................................... 355
7.1.2 FSB Dynamic Bus Inversion ................................................................... 355
7.1.3 FSB Interrupt Overview......................................................................... 356
Snoop Filter.................................................................................................... 356
System Memory Controller ............................................................................... 358
7.3.1 Fully Buffered DIMM Technology and Organization .................................... 360
7.3.2 FB-DIMM Memory Configuration Mechanism ............................................. 362
7.3.3 DDR2 Protocol ..................................................................................... 364
7.3.4 FB-DIMM Memory Operating Modes ........................................................ 365
7.3.5 Memory Population Rules ...................................................................... 366
7.3.6 ECC Code ............................................................................................ 369
7.3.7 Single Device Data Correction (SDDC) Support......................................... 371
7.3.8 x8 Correction....................................................................................... 372
7.3.9 Demand Scrubbing ............................................................................... 373
7.3.10 Patrol Scrubbing................................................................................... 373
7.3.11 Data Poisoning in Memory ..................................................................... 374
7.3.12 Memory Mirroring ................................................................................. 374
7.3.13 DIMM Sparing ...................................................................................... 374
7.3.14 FB-DIMM Power Management................................................................. 375
7.3.15 FBD Throttling ..................................................................................... 375
7.3.16 FB-DIMM IBIST Support ........................................................................ 379
Interrupts ...................................................................................................... 379
7.4.1 XAPIC Interrupt Message Delivery .......................................................... 379
7.4.2 I/O Interrupts ...................................................................................... 384
7.4.3 Interprocessor Interrupts (IPIs) ............................................................. 386
7.4.4 Chipset Generated Interrupts................................................................. 387
7.4.5 Generation of MSIs............................................................................... 389
7.4.6 Legacy PCI-style INTx Message Handling ................................................. 390
7.4.7 SMI .................................................................................................... 391
7.4.8 Interrupt Error Handling ........................................................................ 392
PCI Express General Purpose Ports .................................................................... 392
7.5.1 PCI Express Port Support Summary ........................................................ 393
7.5.2 PCI Express Port Physical Layer Characteristics ........................................ 394
7.5.3 Link Layer ........................................................................................... 398
7.5.4 Flow Control ........................................................................................ 400
7.5.5 Transaction Layer................................................................................. 403
7.5.6 Stream/Port Arbitration......................................................................... 404
7.5.7 Supported PCI Express Transactions ....................................................... 404
7.5.8 Transaction Descriptor .......................................................................... 407
7.5.9 Transaction Behavior ............................................................................ 408
7.5.10 Ordering Rules ..................................................................................... 412
7.5.11 Prefetching Policies............................................................................... 415
7.5.12 No Isochronous Support ........................................................................ 415
7.5.13 PCI Express Hot-Plug ............................................................................ 415
7.5.14 Error Handling ..................................................................................... 416
7.5.15 PCI Express Power Management Support ................................................. 417
Enterprise South Bridge Interface (ESI).............................................................. 419
7.6.1 Peer-to-Peer Support ............................................................................ 420
7.6.2 Power Management Support .................................................................. 421
7.6.3 Special Interrupt Support ...................................................................... 421
7.6.4 Inbound Interrupts ............................................................................... 422
7.6.5 Legacy Interrupt Messages .................................................................... 422
7.6.6 End-of-Interrupt (EOI) Support .............................................................. 422
7.6.7 Error Handling ..................................................................................... 422
Intel® QuickData Technology ........................................................................... 423
Intel
®
7300 Chipset Memory Controller Hub (MCH) Datasheet
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