Intel
®
865G/865GV Chipset
Datasheet
Intel
®
82865G/82865GV Graphics and Memory Controller Hub
(GMCH)
February 2004
Document Number: 252514-005
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®
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®
82865G/82865GV GMCH may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
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2003–2004, Intel Corporation
2
Intel
®
82865G/82865GV GMCH Datasheet
Contents
1
Introduction
...........................................................................................................15
1.1
1.2
1.3
1.4
Terminology ...................................................................................................16
Related Documents .......................................................................................17
Intel
®
865G Chipset System Overview ..........................................................18
Intel
®
82865G GMCH Overview ....................................................................20
1.4.1 Host Interface....................................................................................20
1.4.2 System Memory Interface .................................................................20
1.4.3 Hub Interface ....................................................................................21
1.4.4 Communications Streaming Architecture (CSA) Interface ................21
1.4.5 Multiplexed AGP and Intel
®
DVO Interface.......................................21
1.4.6 Graphics Overview............................................................................22
1.4.7 Display Interface ...............................................................................24
Clock Ratios...................................................................................................24
Host Interface Signals....................................................................................27
Memory Interface ...........................................................................................30
2.2.1 DDR SDRAM Channel A ..................................................................30
2.2.2 DDR SDRAM Channel B ..................................................................31
Hub Interface .................................................................................................32
Communication Streaming Architecture (CSA) Interface...............................32
AGP Interface ................................................................................................33
2.5.1 AGP Addressing Signals...................................................................33
2.5.2 AGP Flow Control Signals ................................................................34
2.5.3 AGP Status Signals ..........................................................................34
2.5.4 AGP Strobes .....................................................................................35
2.5.5 PCI Signals–AGP Semantics............................................................36
2.5.5.1 PCI Pins during PCI Transactions on AGP Interface ........37
2.5.6 Multiplexed Intel
®
DVOs on AGP ......................................................37
2.5.7 Intel
®
DVO-to-AGP Pin Mapping.......................................................39
Analog Display Interface ................................................................................40
Clocks, Reset, and Miscellaneous Signals ....................................................41
RCOMP, VREF, VSWING Signals.................................................................42
Power and Ground Signals ............................................................................43
GMCH Sequencing Requirements.................................................................44
Signals Used As Straps .................................................................................45
2.11.1 Functional Straps ..............................................................................45
2.11.2 Strap Input Signals............................................................................45
Full and Warm Reset States ..........................................................................46
Register Terminology.....................................................................................47
Platform Configuration Structure....................................................................48
Routing Configuration Accesses....................................................................50
3.3.1 Standard PCI Bus Configuration Mechanism ...................................50
3.3.2 PCI Bus #0 Configuration Mechanism ..............................................50
3.3.3 Primary PCI and Downstream Configuration Mechanism.................50
3.3.4 AGP/PCI_B Bus Configuration Mechanism ......................................51
1.5
2
Signal Description
..............................................................................................25
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
3
Register Description
..........................................................................................47
3.1
3.2
3.3
Intel
®
82865G/82865GV GMCH Datasheet
3
3.4
3.5
3.6
I/O Mapped Registers.................................................................................... 52
3.4.1 CONFIG_ADDRESS—Configuration Address Register ................... 53
3.4.2 CONFIG_DATA—Configuration Data Register ................................ 54
DRAM Controller/Host-Hub Interface Device Registers (Device 0) ............... 55
3.5.1 VID—Vendor Identification Register (Device 0)................................ 57
3.5.2 DID—Device Identification Register (Device 0) ................................ 57
3.5.3 PCICMD—PCI Command Register (Device 0)................................. 58
3.5.4 PCISTS—PCI Status Register (Device 0) ........................................ 59
3.5.5 RID—Revision Identification Register (Device 0) ............................. 60
3.5.6 SUBC—Sub-Class Code Register (Device 0) .................................. 60
3.5.7 BCC—Base Class Code Register (Device 0) ................................... 60
3.5.8 MLT—Master Latency Timer Register (Device 0)............................. 61
3.5.9 HDR—Header Type Register (Device 0) .......................................... 61
3.5.10 APBASE—Aperture Base Configuration Register (Device 0)........... 62
3.5.11 SVID—Subsystem Vendor Identification Register (Device 0)........... 63
3.5.12 SID—Subsystem Identification Register (Device 0).......................... 63
3.5.13 CAPPTR—Capabilities Pointer Register (Device 0) ......................... 63
3.5.14 AGPM—AGP Miscellaneous Configuration Register
(Device 0) ......................................................................................... 64
3.5.15 GC—Graphics Control Register (Device 0) ...................................... 65
3.5.16 CSABCONT—CSA Basic Control Register (Device 0)..................... 67
3.5.17 FPLLCONT— Front Side Bus PLL Clock Control Register
(Device 0) ......................................................................................... 68
3.5.18 PAM[0:6]—Programmable Attribute Map Registers
(Device 0) ......................................................................................... 69
3.5.19 FDHC—Fixed Memory(ISA) Hole Control Register
(Device 0) ......................................................................................... 71
3.5.20 SMRAM—System Management RAM Control Register
(Device 0) ......................................................................................... 72
3.5.21 ESMRAMC—Extended System Management RAM Control
(Device 0) ......................................................................................... 73
3.5.22 ACAPID—AGP Capability Identifier Register (Device 0) .................. 74
3.5.23 AGPSTAT—AGP Status Register (Device 0) ................................... 74
3.5.24 AGPCMD—AGP Command Register (Device 0).............................. 76
3.5.25 AGPCTRL—AGP Control Register (Device 0) ................................. 77
3.5.26 APSIZE—Aperture Size Register (Device 0) .................................... 78
3.5.27 ATTBASE—Aperture Translation Table Register (Device 0)............ 78
3.5.28 AMTT—AGP MTT Control Register (Device 0) ................................ 79
3.5.29 LPTT—AGP Low Priority Transaction Timer Register
(Device 0) ......................................................................................... 80
3.5.30 TOUD—Top of Used DRAM Register (Device 0) ............................. 81
3.5.31 GMCHCFG—GMCH Configuration Register (Device 0)................... 82
3.5.32 ERRSTS—Error Status Register (Device 0)..................................... 84
3.5.33 ERRCMD—Error Command Register (Device 0) ............................. 85
3.5.34 SKPD—Scratchpad Data Register (Device 0) .................................. 86
3.5.35 CAPREG—Capability Identification Register (Device 0) .................. 86
PCI-to-AGP Bridge Configuration Register (Device 1) .................................. 87
3.6.1 VID1—Vendor Identification Register (Device 1).............................. 88
3.6.2 DID1—Device Identification Register (Device 1) .............................. 88
3.6.3 PCICMD1—PCI Command Register (Device 1)............................... 89
3.6.4 PCISTS1—PCI Status Register (Device 1) ...................................... 90
3.6.5 RID1—Revision Identification Register (Device 1) ........................... 91
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Intel
®
82865G/82865GV GMCH Datasheet
3.7
SUBC1—Sub-Class Code Register (Device 1) ................................91
BCC1—Base Class Code Register (Device 1) .................................91
MLT1—Master Latency Timer Register (Device 1)...........................92
HDR1—Header Type Register (Device 1) ........................................92
PBUSN1—Primary Bus Number Register (Device 1) .......................92
SBUSN1—Secondary Bus Number Register (Device 1) ..................93
SUBUSN1—Subordinate Bus Number Register (Device 1) .............93
SMLT1—Secondary Bus Master Latency Timer Register
(Device 1)..........................................................................................93
3.6.14 IOBASE1—I/O Base Address Register (Device 1) ...........................94
3.6.15 IOLIMIT1—I/O Limit Address Register (Device 1) ............................94
3.6.16 SSTS1—Secondary Status Register (Device 1) ...............................95
3.6.17 MBASE1—Memory Base Address Register (Device 1)....................96
3.6.18 MLIMIT1—Memory Limit Address Register (Device 1).....................97
3.6.19 PMBASE1—Prefetchable Memory Base Address Register
(Device 1)..........................................................................................98
3.6.20 PMLIMIT1—Prefetchable Memory Limit Address Register
(Device 1)..........................................................................................98
3.6.21 BCTRL1—Bridge Control Register (Device 1) ..................................99
3.6.22 ERRCMD1—Error Command Register (Device 1) .........................100
Integrated Graphics Device Registers (Device 2)........................................101
3.7.1 VID2—Vendor Identification Register (Device 2) ............................102
3.7.2 DID2—Device Identification Register (Device 2) ............................102
3.7.3 PCICMD2—PCI Command Register (Device 2) .............................103
3.7.4 PCISTS2—PCI Status Register (Device 2) ....................................104
3.7.5 RID2—Revision Identification Register (Device 2) .........................104
3.7.6 CC—Class Code Register (Device 2) .............................................105
3.7.7 CLS—Cache Line Size Register (Device 2) ...................................105
3.7.8 MLT2—Master Latency Timer Register (Device 2).........................105
3.7.9 HDR2—Header Type Register (Device 2) ......................................106
3.7.10 GMADR—Graphics Memory Range Address Register
(Device 2)........................................................................................106
3.7.11 MMADR—Memory-Mapped Range Address Register
(Device 2)........................................................................................107
3.7.12 IOBAR—I/O Decode Register (Device 2) .......................................107
3.7.13 SVID2—Subsystem Vendor Identification Register
(Device 2)........................................................................................108
3.7.14 SID2—Subsystem Identification Register (Device 2)......................108
3.7.15 ROMADR—Video BIOS ROM Base Address Registers
(Device 2)........................................................................................108
3.7.16 CAPPOINT—Capabilities Pointer Register (Device 2) ...................109
3.7.17 INTRLINE—Interrupt Line Register (Device 2) ...............................109
3.7.18 INTRPIN—Interrupt Pin Register (Device 2)...................................109
3.7.19 MINGNT—Minimum Grant Register (Device 2) ..............................110
3.7.20 MAXLAT—Maximum Latency Register (Device 2) .........................110
3.7.21 PMCAPID—Power Management Capabilities Identification
Register (Device 2) .........................................................................110
3.7.22 PMCAP—Power Management Capabilities Register
(Device 2)........................................................................................111
3.7.23 PMCS—Power Management Control/Status Register
(Device 2)........................................................................................111
3.7.24 SWSMI—Software SMI Interface Register (Device 2) ....................112
3.6.6
3.6.7
3.6.8
3.6.9
3.6.10
3.6.11
3.6.12
3.6.13
Intel
®
82865G/82865GV GMCH Datasheet
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