3.3V and 5.0V pASIC 2 FPGA
Combining Speed, Density, Low Cost and Flexibility
Rev. C
pASIC 2
HIGHLIGHTS
®
QL2003
Ultimate Verilog/VHDL Silicon Solution
-Abundant, high-speed interconnect eliminates manual routing
-Flexible logic cell provides high efficiency
and
performance
-Design tools produce fast, efficient Verilog/VHDL synthesis
Speed, Density, Low Cost and Flexibility in One Device
… 3,000
usable ASIC gates,
118 I/O pins
-16-bit counter speeds exceeding 200 MHz
-3,000 usable ASIC gates, 5,000 usable PLD gates, 118 I/Os
-3-layer metal ViaLink
®
process for small die sizes
-100% routable and pin-out maintainable
3
pASIC 2
Advanced Logic Cell and I/O Capabilities
-Complex functions (up to 16 inputs) in a single logic cell
-High synthesis gate utilization from logic cell fragments
-Full IEEE Standard JTAG boundary scan capability
-Individually-controlled input/feedback registers and OEs on all I/O pins
Other Important Family Features
-3.3V and 5.0V operation with low standby power
-I/O pin-compatibility between different devices in the same packages
-PCI compliant (at 5.0V), full speed 33 MHz implementations
-High design security provided by security fuses
QL2003
Block Diagram
192
Logic
Cells
3-5
QL2003
PRODUCT
SUMMARY
The QL2003 is a 3,000 usable ASIC gate, 5,000 usable PLD gate member of
the pASIC 2 family of FPGAs. pASIC 2 FPGAs employ a unique
combination of architecture, technology, and software tools to provide high
speed, high usable density, low price, and flexibility in the same devices.
The flexibility and speed make pASIC 2 devices an efficient and high
performance silicon solution for designs described using HDLs such as
Verilog and VHDL, as well as schematics.
The QL2003 contains 192 logic cells. With 118 maximum I/Os, the
QL2003 is available in 84-PLCC, 100-pin TQFP and 144-pin TQFP
packages.
Software support for the complete pASIC families, including the QL2003, is
available through three basic packages. The turnkey QuickWorks
®
package
provides the most complete FPGA software solution from design entry to
logic synthesis (by Synplicity, Inc.), to place and route, to simulation. The
QuickTools
TM
and QuickChip
TM
packages provide a solution for designers
who use Cadence, Mentor, Synopsys, Viewlogic, Veribest, or other third-
party tools for design entry, synthesis, or simulation.
FEATURES
Total of 118 I/O Pins
- 110 bidirectional input/output pins, PCI-compliant at 5.0V
in -1/-2 speed grades
- 4 high-drive input-only pins
- 4 high-drive input/distributed network pins
Four Low-Skew (less than 0.5ns) Distributed Networks
- Two array networks available to logic cell flip-flop clock, set, and
reset - each driven by an input-only pin
- Two global clock/control networks available to F1 logic input, and
logic cell flip-flop clock, set, reset; input and I/O register clock, reset,
enable; and output enable controls - each driven by an input-only pin,
or any input or I/O pin, or any logic cell output or I/O cell feedback
High Performance
- Input + logic cell + output delays under 6 ns
- Datapath speeds exceeding 225 MHz
- Counter speeds over 200 MHz
3-6
QL2003
PINOUT DIAGRAM
84-PIN PLCC
3
pASIC 2
3-7
QL2003
PINOUT DIAGRAMS
PIN # 76
PIN # 1
100-PIN TQFP
pASIC
QL2003-1PF100C
PIN # 51
PIN # 26
144-PIN TQFP
PIN # 1
PIN # 109
pASIC
QL2003-1PF144C
PIN # 73
PIN # 37
3-8
QL2003
100 and 144 TQFP Pinout Table
144
100
TQFP TQFP
1
2
2
NC
3
3
4
4
5
NC
6
5
7
NC
8
6
9
NC
10
7
11
NC
12
NC
13
8
14
NC
15
9
16
10
17
11
18
12
19
13
20
14
21
15
22
16
23
17
24
18
25
NC
26
19
27
NC
28
20
29
21
Function
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I
ACLK / I
VCC
I
GCLK / I
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
144
100
TQFP TQFP
30
NC
31
NC
32
22
33
NC
34
23
35
NC
36
24
37
25
38
26
39
27
40
28
41
29
42
NC
43
30
44
31
45
NC
46
32
47
33
48
NC
49
34
50
35
51
36
52
NC
53
37
54
38
55
39
56
40
57
41
58
42
Function
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDI
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCC
144
100
TQFP TQFP
59
NC
60
43
61
44
62
45
63
NC
64
NC
65
46
66
NC
67
NC
68
NC
69
47
70
48
71
49
72
50
73
51
74
52
75
53
76
54
77
55
78
NC
79
NC
80
NC
81
56
82
NC
83
57
84
NC
85
58
86
NC
87
59
Function
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
TRSTB
TMS
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
144
100
TQFP TQFP
88
60
89
61
90
62
91
63
92
64
93
65
94
66
95
67
96
NC
NC
68
97
NC
98
69
99
NC
100
70
101
71
102
NC
103
NC
104
72
105
NC
106
73
107
74
108
75
109
76
110
77
111
78
112
79
113
80
114
NC
115
81
Function
I/O
I
ACLK / I
VCC
I
GCLK / I
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
TCK
STM
I/O
I/O
I/O
VCC
I/O
144
100
TQFP TQFP
116
82
117
83
118
NC
119
84
120
NC
121
NC
122
85
123
NC
124
86
125
87
126
88
127
89
128
90
129
91
130
92
131
NC
132
93
133
NC
134
94
135
NC
136
NC
137
95
138
NC
139
96
140
97
141
98
142
99
143
100
144
1
Function
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
TDO
I/O
3
pASIC 2
3-9
