QuickLogic
®
PolarPro
®
II
Device Data Sheet
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Combining Low Power Programmable Fabric and Embedded SRAM
• Quadrant-based segmentable clock networks
Device Highlights
Low Power Programmable Logic
• Up to 27 customizable building blocks (CBBs) for
a detailed explanation of CBBs)
• Up to 27 kilobits of SRAM
• One user configurable clock manager (CCM)
• As low as 4.2 µA standby current
• 0.18 µm, six layer metal CMOS process
• 1.5 V or 1.8 V core voltage, 1.8/2.5/3.3 V drive
capable I/Os
• Up to 103 I/Os available
• Up to 150,000 system gates
• Nonvolatile, instant-on
• IEEE 1149.1 boundary scan testing compliant
20 quad clock networks per device
4 quad clock networks per quadrant
1 dedicated clock network per quadrant
• One user Configurable Clock Manager (CCM)
Very Low Power (VLP) Mode
• QuickLogic PolarPro II device has a special VLP
pin which can enable a low power sleep mode
that significantly reduces the overall power
consumption of the device by placing the device in
standby
• Enter/exit VLP mode from/to normal operation
in less than 10 µs (typical)
JTAG
QuickLogic PolarPro II family of solution platforms
supports IEEE 1149.1 boundary scan or post-
manufacturing testability. External access to this
feature can be completely disabled.
Embedded Dual-Port SRAM
• Up to four dual-port 4-kilobit and four 2-kilobit
high performance SRAM blocks
• True dual-port capability for RAM and FIFOs
• Embedded synchronous/asynchronous FIFO
controller
• Configurable and cascadable aspect ratio
Security Links
There are several security links to disable JTAG
access to the device. Programming these optional
links completely disables access to the device from
the outside world and provides an extra level of
design security not possible in SRAM-based FPGAs.
Figure 1: QuickLogic PolarPro II Block Diagram
GPIO
GPIO
GPIO
GPIO
Programmable I/O
• Eight independent I/O banks capable of
supporting multiple I/O standards in one device
• Bank programmable I/O standards: LVTTL,
LVCMOS, LVCMOS18, and PCI
GPIO
GPIO
CCM
GPIO
• Individual programmable slew rate control
Embedded RAM Blocks
FIFO Controller
Fabric
GPIO
GPIO
Advanced Clock Network
• Multiple low skew clock networks
GPIO
4 programmable global clock networks
Embedded RAM Blocks
GPIO
GPIO
GPIO
GPIO
GPIO
1 dedicated global clock network
FIFO Controller
GPIO
© 2013 QuickLogic Corporation
www.quicklogic.com
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QuickLogic
®
PolarPro
®
II Device Data Sheet Rev. 1.0
Ultra-Low Power FPGA Combining Performance, Density, and
Embedded SRAM
Table 1
summarizes the PolarPro II device family features.
Table 1: PolarPro II Device QL2P150
Features
Max Gates
Logic Cells
RAM Modules
FIFO Controllers
RAM bits
CCMs
144 VFBGA (0.4 mm pitch)
Max I/O per
Package
121 TFBGA (0.5 mm pitch)
64 WLCSP (0.4 mm pitch)
QL2P150
150,000
864
8
8
27,648
1
103
81
41
Process Data
The QuickLogic PolarPro II is fabricated on a 0.18µ, six layer metal CMOS process. The core voltage is 1.5 V
or 1.8 V. The I/O voltage input tolerance and output drive can be set as 1.8 V, 2.5 V, and 3.3 V.
Programmable Logic Architectural Overview
The QuickLogic PolarPro II logic cell structure presented in
Figure 2
is a single register, multiplexer-based logic
cell. It is designed for wide fan-in and multiple, simultaneous output functions. The cell has a high fan-in, fits
a wide range of functions with up to 24 simultaneous inputs (including register control lines), and four outputs
(three combinatorial and one registered). The high logic capacity and fan-in of the logic cell accommodates
many user functions with a single level of logic delay.
The QuickLogic PolarPro II logic cell can implement:
• Two independent 3-input functions
• Any 4-input function
• 8 to 1 mux function
• Independent 2 to 1 mux function
• Single dedicated register with clock enable, active high set and reset signals
• Direct input selection to the register, which allows combinatorial and register logic to be used separately
• Combinatorial logic that can also be configured as an edge-triggered master-slave D flip-flop
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© 2013 QuickLogic Corporation
QuickLogic
®
PolarPro
®
II Device Data Sheet Rev. 1.0
Figure 2: PolarPro II Logic Cell
QST
QDS
TBS
TAB
TSL
TI
TA1
TA2
TB1
TB2
BAB
BSL
BI
BA1
BA2
BB1
BB2
FS
F1
F2
QDI
QEN
QCK
QRT
TZ
0
1
0
1
0
1
0
1
0
1
CZ
S
D
E
Q
QZ
0
1
0
1
0
1
R
0
1
FZ
RAM Modules
The PolarPro II QL2P150 device has four 4-kilobit (4608 bits) as shown in
Figure 3,
and four 2-kilobit (2304)
RAM blocks as shown in
Figure 4.
The RAM features include:
• Independently configurable read and write data bus widths
• Independent read and write clocks
• Maximum of two RAM blocks can be concatenated horizontally or vertically
4 kilobits for two 2-kilobit RAM blocks and 8 kilobits for two 4-kilobit RAM blocks
• Write byte enables
• Selectable pipelined or non-pipelined read data
• True dual-port RAM functionality
• Clock disabling during idle operation
© 2013 QuickLogic Corporation
www.quicklogic.com
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QuickLogic
®
PolarPro
®
II Device Data Sheet Rev. 1.0
Figure 3: 4-Kilobit Dual-Port RAM Block
WD[17:0]
WA[7:0]
WEN[1:0]
WD_SEL
WCLK
WCLK_EN
RA[7:0]
RD_SEL
RCLK
RCLK_EN
RD[17:0]
Figure 4: 2-Kilobit Dual-Port RAM Block
WD[8:0]
WA[7:0]
WEN[1:0]
WD_SEL
WCLK
WCLK_EN
RA[7:0]
RD_SEL
RCLK
RCLK_EN
RD[8:0]
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© 2013 QuickLogic Corporation
QuickLogic
®
PolarPro
®
II Device Data Sheet Rev. 1.0
Table 2
describes the RAM interface signals.
Table 2: RAM Interface Signals
Signal Name
Inputs
WD
WA
WEN
WD_SEL
WCLK
WCLK_EN
RA
RD_SEL
RCLK
RCLK_EN
RD
Write Data
Write Address
Write Enable
Write Chip Select
Write Clock
Write Clock Enable
Read Address
Read Chip Select
Read Clock
Read Clock Enable
Output
Read Data
Function
The read and write data buses of a RAM block can be arranged to variable bus widths. The bus widths can be
configured using the RAM Wizard available in QuickWorks, QuickLogic’s development software. The selection
of the RAM depth and width determines how the data is addressed.
The RAM blocks also support data concatenation. Designers can cascade multiple RAM modules to increase
the depth or width by connecting corresponding address lines together and dividing the words between
modules. Generally, this requires the use of additional programmable logic resources. However, when
concatenating only two 4-kilobit RAM blocks or two 2-kilobit RAM blocks, they can be concatenated
horizontally or vertically without using any additional programmable fabric resources.
For example, two internal 4-kilobit dual-port RAM blocks can be concatenated vertically to create a 512x18
RAM block or horizontally to create a 256x36 RAM block.
Figure 5
displays a block diagram of 4-kilobit RAM
blocks horizontal and vertical concatenation.
© 2013 QuickLogic Corporation
www.quicklogic.com
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