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QL3040 - pASIC 3 FPGA

40,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance

and

High Density

QL3040 - pASIC 3 FPGA

EVICE

IGHLIGHTS

Device Highlights

High Performance & High Density

40,000 Usable PLD Gates with 252 I/Os

16-bit counter speeds over 300 MHz, data path speeds over

400 MHz

0.35um four-layer metal non-volatile CMOS process for

smallest die sizes

Easy to Use / Fast Development Cycles

100% routable with 100% utilization and complete

pin-out stability

Variable-grain logic cells provide high performance and

100% utilization

Comprehensive design tools include high quality

Verilog/VHDL synthesis

Advanced I/O Capabilites

Interfaces with both 3.3V and 5.0V devices

PCI compliant with 3.3V and 5.0V buses for -1/-2/-3/-4

FIGURE 1. 1,008 Logic Cells

speed grades

Full JTAG boundary scan

Registered I/O cells with individually controlled clocks and

RODUCT

UMMARY

Product Summary

output enables

Total of 252 I/O Pins

244 bidirectional input/output pins, PCI-compliant for 5.0V and

3.3V buses for -1/-2/-3/-4 speed grades

8 high-drive input/distributed network pins

The QL3040 is a 40,000 usable PLD gate member of

the pASIC 3 family of FPGAs. pASIC 3 FPGAs are

fabricated on a 0.35mm four-layer metal process

using QuickLogic’s patented ViaLink technology to

provide a unique combination of high performance,

high density, low cost, and extreme ease-of-use.

The QL3040 contains 1,008 logic cells. With a

maximum of 252 I/Os, the QL3040 is available in

208-PQFP and 456-pin PBGA packages.

Software support for the complete pASIC 3 family,

including the QL3040, is available through three basic

packages. The turnkey QuickWorks“ package

provides the most complete FPGA software solution

from design entry to logic synthesis, to place and

route, to simulation. The QuickChipTM and

QuickToolsTM packages provide a solution for

designers who use Cadence, Exemplar, Mentor,

Synopsys, Synplicity, Viewlogic, Veribest, or other

third-party tools for design entry, synthesis, or

simulation.

Eight Low-Skew Distributed Networks

Two array clock/control networks available to the logic cell flip-

flop clock, set and reset inputs - each driven by an input-only pin

Six global clock/control networks available to the logic cell F1,

clock set and reset inputs and the input and I/O register clock,

reset and enable inputs as well as the output enable control - each

driven by an input-only or I/O pin, or any logic cell output or I/O

cell feedback

High Performance

Input + logic cell + output total delays under 6 ns

Data path speeds over 400 MHz

Counter speeds over 300 MHz

QL3040 Rev D

8-267

QL3040 - pASIC 3 FPGA

208-P

PQFP P

INOUT

IAGRAM

ASIC P

INOUT

IAGRAM

208-Pin PQFP Pinout Diagrams

Pin #1

Pin #157

pASIC

QL3040-1PQ208C

Pin #53

FIGURE 2. 208-Pin PQFP

Pin #105

8-268

268

Preliminary

QL3040 - pASIC 3 FPGA

208 PQFP P

INOUT

ABLE

208 PQFP Pinout Table

208

PQFP

208

Function

I/O

VCC

I/O

GND

I/O

GND

I/O

GCLK/I

VCC

GCLK/I

VCC

I/O

GND

I/O

VCC

I/O

208

PQFP

Function

GND

I/O

TDI

I/O

GND

I/O

VCC

I/O

GND

I/O

VCC

I/O

GND

I/O

VCCIO

208

PQFP

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

Function

I/O

GND

I/O

VCC

I/O

TRSTB

TMS

I/O

VCC

I/O

GND

I/O

208

PQFP

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

Function

I/O

GND

I/O

GCLK/I

ACLK/I

VCC

GCLK/I

VCC

I/O

GND

I/O

VCC

I/O

GND

I/O

TCK

STM

I/O

GND

I/O

VCC

I/O

208

PQFP

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

Function

I/O

GND

I/O

GND

VCC

I/O

VCCIO

I/O

GND

I/O

VCC

I/O

TDO

8-269

QL3040 - pASIC 3 FPGA

456-P

PBGA

INOUT

IAGRAM

456-Pin PBGA Pinout Diagram

pASIC

QL3040-1PB456C

TOP

Pin A1 Corner

20 18

10 8

BOTTOM

8-270

270

Preliminary

QL3040 - pASIC 3 FPGA

PBGA 456 P

INOUT

ABLE

PBGA 456 Pinout Table

456

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

Function

I/O

VCCIO

I/O

456

B26

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

Function

STM

I/O

TDO

I/O

TCK

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

456

D25

D26

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

F22

F23

F24

F25

F26

G22

G23

G24

G25

G26

Function

I/O

GND

VCC

GND

I/O

GND

VCC

GND

VCC

GND

I/O

VCC

I/O

GND

I/O

456

H22

H23

H24

H25

H26

J22

J23

J24

J25

J26

K22

K23

K24

K25

K26

L11

L12

L13

L14

L15

L16

L22

L23

L24

L25

L26

M11

M12

M13

Function

I/O

GND

I/O

VCC

GND

I/O

GND/THERM

I/O

ACLK / I

GCLK/I

I/O

GND

GND/THERM

456

M14

M15

M16

M22

M23

M24

M25

M26

N11

N12

N13

N14

N15

N16

N22

N23

N24

N25

N26

P11

P12

P13

P14

P15

P16

P22

P23

P24

P25

P26

R11

R12

R13

R14

R15

R16

Function

GND/THERM

I/O

GCLK/I

I/O

GCLK/I

VCC

GND/THERM

GND

I/O

GND/THERM

GCLK / I

ACLK / I

I/O

GND/THERM

(continued next page)

8-271

参数对比

与QL3040-0PQ208M相近的元器件有：QL3040-0PB456C、QL3040-3PB456C、QL3040-0PB456M、QL3040-2PQ208C、QL3040-2PQ208M、QL3040-4PQ208M、QL3040-4PB456I、QL3040-2PQ208I、QL3040-3PQ208I。描述及对比如下：

型号	QL3040-0PQ208M	QL3040-0PB456C	QL3040-3PB456C	QL3040-0PB456M	QL3040-2PQ208C	QL3040-2PQ208M	QL3040-4PQ208M	QL3040-4PB456I	QL3040-2PQ208I	QL3040-3PQ208I
描述	Field Programmable Gate Array, 1008 CLBs, 40000 Gates, 1008-Cell, CMOS, PQFP208, 28 X 28 MM, 3.35 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MS-029, QFP-208	Field Programmable Gate Array, 1008 CLBs, 40000 Gates, 225MHz, 1008-Cell, CMOS, PBGA456, 35 X 35 MM, 2.33 MM HIEGHT, 1.27 MM PITCH, PLASTIC, MS-034BAR-2, BGA-456	Field Programmable Gate Array, 1008 CLBs, 40000 Gates, 225MHz, 1008-Cell, CMOS, PBGA456, 35 X 35 MM, 2.33 MM HIEGHT, 1.27 MM PITCH, PLASTIC, MS-034BAR-2, BGA-456	Field Programmable Gate Array, 1008 CLBs, 40000 Gates, 1008-Cell, CMOS, PBGA456, 35 X 35 MM, 2.33 MM HIEGHT, 1.27 MM PITCH, PLASTIC, MS-034BAR-2, BGA-456	Field Programmable Gate Array, 1008 CLBs, 40000 Gates, 225MHz, 1008-Cell, CMOS, PQFP208, 28 X 28 MM, 3.35 MM HEIGHT, PLASTIC, MS-029, QFP-208	Field Programmable Gate Array, 1008 CLBs, 40000 Gates, 225MHz, 1008-Cell, CMOS, PQFP208, 28 X 28 MM, 3.35 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MS-029, QFP-208	Field Programmable Gate Array, 1008 CLBs, 40000 Gates, 1008-Cell, CMOS, PQFP208, 28 X 28 MM, 3.35 MM HEIGHT, PLASTIC, MS-029, QFP-208	Field Programmable Gate Array, 1008 CLBs, 40000 Gates, 377.1MHz, 1008-Cell, CMOS, PBGA456, 35 X 35 MM, 2.33 MM HIEGHT, 1.27 MM PITCH, PLASTIC, MS-034BAR-2, BGA-456	Field Programmable Gate Array, 1008 CLBs, 40000 Gates, 225MHz, 1008-Cell, CMOS, PQFP208, 28 X 28 MM, 3.35 MM HEIGHT, PLASTIC, MS-029, QFP-208	Field Programmable Gate Array, 1008 CLBs, 40000 Gates, 225MHz, 1008-Cell, CMOS, PQFP208, 28 X 28 MM, 3.35 MM HEIGHT, PLASTIC, MS-029, QFP-208
是否无铅	含铅	含铅	含铅	含铅	含铅	含铅	含铅	含铅	含铅	含铅
是否Rohs认证	不符合	不符合	不符合	不符合	不符合	不符合	不符合	不符合	不符合	不符合
厂商名称	QuickLogic Corporation	QuickLogic Corporation	QuickLogic Corporation	QuickLogic Corporation	QuickLogic Corporation	QuickLogic Corporation	QuickLogic Corporation	QuickLogic Corporation	QuickLogic Corporation	QuickLogic Corporation
零件包装代码	QFP	BGA	BGA	BGA	QFP	QFP	QFP	BGA	QFP	QFP
包装说明	28 X 28 MM, 3.35 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MS-029, QFP-208	BGA, BGA456,26X26,50	BGA, BGA456,26X26,50	BGA, BGA456,26X26,50	28 X 28 MM, 3.35 MM HEIGHT, PLASTIC, MS-029, QFP-208	28 X 28 MM, 3.35 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MS-029, QFP-208	28 X 28 MM, 3.35 MM HEIGHT, PLASTIC, MS-029, QFP-208	BGA, BGA456,26X26,50	28 X 28 MM, 3.35 MM HEIGHT, PLASTIC, MS-029, QFP-208	28 X 28 MM, 3.35 MM HEIGHT, PLASTIC, MS-029, QFP-208
针数	208	456	456	456	208	208	208	456	208	208
Reach Compliance Code	compli	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant
JESD-30 代码	S-PQFP-G208	S-PBGA-B456	S-PBGA-B456	S-PBGA-B456	S-PQFP-G208	S-PQFP-G208	S-PQFP-G208	S-PBGA-B456	S-PQFP-G208	S-PQFP-G208
JESD-609代码	e0	e0	e0	e0	e0	e0	e0	e0	e0	e0
长度	28 mm	35 mm	35 mm	35 mm	28 mm	28 mm	28 mm	35 mm	28 mm	28 mm
湿度敏感等级	3	3	3	3	3	3	3	3	3	3
可配置逻辑块数量	1008	1008	1008	1008	1008	1008	1008	1008	1008	1008
等效关口数量	40000	40000	40000	40000	40000	40000	40000	40000	40000	40000
输入次数	252	252	252	252	174	174	252	252	174	174
逻辑单元数量	1008	1008	1008	1008	1008	1008	1008	1008	1008	1008
输出次数	244	244	244	244	166	166	244	244	166	166
端子数量	208	456	456	456	208	208	208	456	208	208
最高工作温度	125 °C	70 °C	70 °C	125 °C	70 °C	125 °C	125 °C	85 °C	85 °C	85 °C
最低工作温度	-55 °C	-	-	-55 °C	-	-55 °C	-55 °C	-40 °C	-40 °C	-40 °C
组织	1008 CLBS, 40000 GATES	1008 CLBS, 40000 GATES	1008 CLBS, 40000 GATES	1008 CLBS, 40000 GATES	1008 CLBS, 40000 GATES	1008 CLBS, 40000 GATES	1008 CLBS, 40000 GATES	1008 CLBS, 40000 GATES	1008 CLBS, 40000 GATES	1008 CLBS, 40000 GATES
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	FQFP	BGA	BGA	BGA	FQFP	FQFP	FQFP	BGA	FQFP	FQFP
封装等效代码	QFP208,1.2SQ,20	BGA456,26X26,50	BGA456,26X26,50	BGA456,26X26,50	QFP208,1.2SQ,20	QFP208,1.2SQ,20	QFP208,1.2SQ,20	BGA456,26X26,50	QFP208,1.2SQ,20	QFP208,1.2SQ,20
封装形状	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
封装形式	FLATPACK, FINE PITCH	GRID ARRAY	GRID ARRAY	GRID ARRAY	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH	GRID ARRAY	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH
峰值回流温度（摄氏度）	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
电源	3.3,3.3/5 V	3.3,3.3/5 V	3.3,3.3/5 V	3.3,3.3/5 V	3.3,3.3/5 V	3.3,3.3/5 V	3.3,3.3/5 V	3.3,3.3/5 V	3.3,3.3/5 V	3.3,3.3/5 V
可编程逻辑类型	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	4.1 mm	2.52 mm	2.52 mm	2.52 mm	4.1 mm	4.1 mm	4.1 mm	2.52 mm	4.1 mm	4.1 mm
最大供电电压	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
最小供电电压	3 V	3 V	3 V	3 V	3 V	3 V	3 V	3 V	3 V	3 V
标称供电电压	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
表面贴装	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	MILITARY	COMMERCIAL	COMMERCIAL	MILITARY	COMMERCIAL	MILITARY	MILITARY	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
端子面层	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
端子形式	GULL WING	BALL	BALL	BALL	GULL WING	GULL WING	GULL WING	BALL	GULL WING	GULL WING
端子节距	0.5 mm	1.27 mm	1.27 mm	1.27 mm	0.5 mm	0.5 mm	0.5 mm	1.27 mm	0.5 mm	0.5 mm
端子位置	QUAD	BOTTOM	BOTTOM	BOTTOM	QUAD	QUAD	QUAD	BOTTOM	QUAD	QUAD
处于峰值回流温度下的最长时间	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
宽度	28 mm	35 mm	35 mm	35 mm	28 mm	28 mm	28 mm	35 mm	28 mm	28 mm
其他特性	MAXIMUM GATES UPTO 48684	CAN ALSO BE OPERATED AT 5.0V	CAN ALSO BE OPERATED AT 5.0V	-	CAN ALSO BE OPERATED AT 5.0V	MAXIMUM GATES UPTO 48684	-	-	CAN ALSO BE OPERATED AT 5.0V	CAN ALSO BE OPERATED AT 5.0V
CLB-Max的组合延迟	6.496 ns	5.92 ns	2.816 ns	-	4 ns	4.384 ns	-	2.624 ns	4.096 ns	2.88 ns
最大时钟频率	-	225 MHz	225 MHz	-	225 MHz	225 MHz	-	377.1 MHz	225 MHz	225 MHz