QL3060 / QL3060R
60,000 Usable PLD Gate pASIC
®
3 FPGA
Combining High Performance
and
High Density
PRELIMINARY DATA
pASIC 3
HIGHLIGHTS
March, 1998
2
High Performance and High Density
-60,000 Usable PLD Gates with 316 I/Os
-16-bit counter speeds over 250 MHz, data path speeds over 275 MHz
-0.35µm four-layer metal non-volatile CMOS process for smallest die sizes
pASIC 3
… 60,000
usable PLD gates,
316 I/O pins
Easy to Use / Fast Development Cycles
-100% routable with 100% utilization and complete pin-out stability
-Variable-grain logic cells provide high performance and 100% utilization
-Comprehensive design tools include high quality Verilog/VHDL synthesis
High Speed Embedded SRAM Available in “R” Versions
-22 dual-port RAM modules, organized in user-configurable 1,152-bit blocks
-5ns access times, each port independently accessible
-Fast and efficient for FIFO, RAM, and ROM functions
Advanced I/O Capabilities
-Interfaces with both 3.3 volt and 5.0 volt devices
-PCI compliant with 3.3V and 5.0V buses for -1/-2/-3/-4 speed grades
-Full JTAG boundary scan
-Registered I/O cells with individually controlled clocks and output enables
QL3060
Block Diagram
1,584
Logic
Cells
2-47
QL3060 / QL3060R
PRODUCT
SUMMARY
The QL3060 is a 60,000 usable PLD gate member of the pASIC 3 family of
FPGAs. pASIC 3 FPGAs are fabricated on a 0.35 m four-layer metal process
using QuickLogic’s patented ViaLink technology to provide a unique
of-use.
The QL3060 contains 1,584 logic cells. With a maximum of 316 I/Os, the
packages. The QL3060R also includes 22 dual port RAM modules, each
with 1,152 bits, for a total of 25,344 RAM bits.
available through three basic packages. The turnkey QuickWorks
®
package
provides the most complete FPGA software solution from design entry to
logic synthesis, to place and route, to simulation. The QuickChip
TM
and
QuickTools
TM
packages provide a solution for designers who use Cadence,
Exemplar, Mentor, Synopsys, Synplicity, Viewlogic, Veribest, or other third-
party tools for design entry, synthesis, or simulation.
FEATURES
Total of 316 I/O Pins
- 308 bidirectional input/output pins, PCI-compliant for
5.0 volt and 3.3 volt buses for -1/-2/-3/-4 speed grades
- 8 high-drive input/distributed network pins
Eight Low-Skew Distributed Networks
- Two array clock/control networks available to the logic cell flip-flop
clock, set and reset inputs - each driven by an input-only pin
- Six global clock/control networks available to the logic cell F1, clock,
set and reset inputs and the input and I/O register clock, reset and
enable
inputs as well as the output enable control - each driven by an input-
only
or I/O pin, or any logic cell output or I/O cell feedback
High Performance
- Input + logic cell + output total delays under 6 ns
- Data path speeds exceeding 275 MHz
- Counter speeds over 250 MHz
2-
QL3060 / QL3060R
PINOUT DIAGRAMS
PIN # 157
208-PIN PQFP
PIN # 1
2
pASIC 3
pASIC
QL3060-1PQ208C
PIN # 53
240-PIN PQFP
PIN # 1
PIN # 105
PIN # 181
p
ASIC
QL3060-1PQ240C
PIN # 61
PIN # 121
2-49
QL3060 / QL3060R
PQFP 240 / 208 Pinout Table
240
208
PQFP PQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
208
1
2
3
4
5
NC
6
7
8
9
10
11
12
13
14
NC
15
16
17
18
19
20
NC
21
22
23
24
25
26
27
28
29
30
31
32
NC
33
NC
34
35
36
NC
37
38
39
NC
40
41
42
Function
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GCLK / I
ACLK / I
VCC
GCLK / I
GCLK / I
VCC
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
240
208
PQFP PQFP
51
52
53
54
55
56
57
58
59
60
NC
NC
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
NC
84
85
86
87
88
89
90
91
92
93
94
95
96
97
43
44
45
46
47
48
NC
49
50
51
52
53
54
NC
NC
55
56
NC
57
58
59
60
61
62
63
64
NC
65
66
67
NC
68
69
70
NC
71
NC
72
73
74
NC
75
76
77
78
79
80
81
82
83
Function
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
VCC
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCCIO
240
208
PQFP PQFP
98
99
100
101
102
103
104
105
106
107
108
109
110
NC
111
NC
NC
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
84
85
86
87
88
89
90
91
92
NC
93
94
95
96
97
98
99
100
NC
101
NC
102
NC
NC
103
104
105
NC
106
107
108
109
NC
110
111
112
113
114
115
116
117
NC
118
119
120
121
NC
122
123
124
Function
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TRSTB
TMS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
240
208 Function 240
208
PQFP PQFP
PQFP PQFP
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
NC
181
182
183
184
185
186
187
188
189
190
191
192
193
125
126
127
128
NC
129
130
131
132
133
134
135
136
NC
137
NC
138
139
140
141
142
NC
143
144
145
NC
146
147
148
149
150
151
152
153
154
155
156
157
158
NC
159
160
161
162
163
164
165
166
NC
167
I/O
I/O
GND
I/O
I/O
GCLK / I
ACLK / I
VCC
GCLK / I
GCLK / I
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK
STM
I/O
I/O
I/O
I/O
I/O
GND
I/O
VCC
I/O
I/O
I/O
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
168
169
NC
170
171
172
173
174
175
NC
176
177
178
179
NC
180
181
182
NC
183
184
185
186
187
188
NC
189
190
191
192
193
194
NC
195
196
197
198
NC
199
200
201
202
203
204
205
206
207
Function
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
VCC
I/O
I/O
I/O
I/O
I/O
TDO
2-50
QL3060 / QL3060R
PINOUT DIAGRAM
456-PIN PBGA
TOP
2
pASIC 3
pASIC
QL3060-1PB456C
BOTTOM
PIN A1
CORNER
2-51
