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QL4009-3PL84C

Field Programmable Gate Array, 160 CLBs, 9000 Gates, 160-Cell, CMOS, PQCC84, PLASTIC, LCC-84

器件类别:可编程逻辑器件    可编程逻辑   

厂商名称:QuickLogic Corporation

厂商官网:https://www.quicklogic.com

下载文档
器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
QuickLogic Corporation
零件包装代码
LCC
包装说明
QCCJ, LDCC84,1.2SQ
针数
84
Reach Compliance Code
compli
CLB-Max的组合延迟
2.816 ns
JESD-30 代码
S-PQCC-J84
JESD-609代码
e0
长度
29.3116 mm
湿度敏感等级
3
可配置逻辑块数量
160
等效关口数量
9000
输入次数
68
逻辑单元数量
160
输出次数
60
端子数量
84
最高工作温度
70 °C
最低工作温度
组织
160 CLBS, 9000 GATES
封装主体材料
PLASTIC/EPOXY
封装代码
QCCJ
封装等效代码
LDCC84,1.2SQ
封装形状
SQUARE
封装形式
CHIP CARRIER
峰值回流温度(摄氏度)
NOT SPECIFIED
电源
3.3,3.3/5 V
可编程逻辑类型
FIELD PROGRAMMABLE GATE ARRAY
认证状态
Not Qualified
座面最大高度
4.57 mm
最大供电电压
3.6 V
最小供电电压
3 V
标称供电电压
3.3 V
表面贴装
YES
技术
CMOS
温度等级
COMMERCIAL
端子面层
Tin/Lead (Sn/Pb)
端子形式
J BEND
端子节距
1.27 mm
端子位置
QUAD
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
29.3116 mm
文档预览
QL4009
9,000 Usable PLD Gate QuickRAM
®
ESP
Combining Performance, Density,
and
Embedded RAM
Last Updated: August 6, 1999
QuickRAM
HIGHLIGHTS
High Performance and High Density
- 9,000 Usable PLD Gates with 82 I/Os
- 300 MHz 16-bit Counters, 400 MHz Datapaths, 160+ MHz FIFOs
- 0.35µm four-layer metal non-volatile CMOS process for smallest die sizes
… 9,000
usable PLD gates,
82 I/O pins
High Speed Embedded SRAM
- 8 dual-port RAM modules, organized in user-configurable 1,152-bit blocks
- 5ns access times, each port independently accessible
- Fast and efficient for FIFO, RAM, and ROM functions
Easy to Use / Fast Development Cycles
- 100% routable with 100% utilization and complete pin-out stability
- Variable-grain logic cells provide high performance and 100% utilization
- Comprehensive design tools include high quality Verilog/VHDL synthesis
Advanced I/O Capabilities
- Interfaces with both 3.3 volt and 5.0 volt devices
- PCI compliant with 3.3V and 5.0V buses for -1/-2/-3/-4 speed grades
- Full JTAG boundary scan
- Registered I/O cells with individually controlled clocks and output enables
QuickRAM
Block Diagram
160 Logic Cells
8 RAM Modules
(9,216 bits)
3-17
QL4009 Rev B
QL4009
PRODUCT
SUMMARY
The QuickRAM family of ESPs (Embedded Standard Products) offers FPGA
logic in combination with Dual-Port SRAM modules. The QL4009 is a 9,000
usable PLD gate member of the QuickRAM family of ESPs. QuickRAM
ESPs are fabricated on a 0.35µm four-layer metal process using QuickLogic’s
patented ViaLink technology to provide a unique combination of high
performance, high density, low cost, and extreme ease-of-use.
The QL4009 contains 160 logic cells and 8 dual port RAM modules. Each
RAM module has 1,152 RAM bits, for a total of 9,216 bits. RAM Modules
are Dual Port (one read port, one write port) and can be configured into one of
four modes: 64 (deep) x18 (wide), 128x9, 256x4, or 512x2. With a maximum
of 82 I/Os, the QL4009 is available in 68-pin PLCC, 84-pin PLCC, and 100-
pin TQFP packages.
Software support for the complete QuickRAM family, including the QL4009,
is available through three basic packages. The turnkey QuickWorks
®
package
provides the most complete ESP software solution from design entry to logic
synthesis, to place and route, to simulation. The QuickWorks
®
-Lite
and
QuickTools
TM
packages provide a solution for designers who use Cadence,
Exemplar, Mentor, Synopsys, Synplicity, Viewlogic, Veribest, or other third-
party tools for design entry, synthesis, or simulation.
FEATURES
Total of 82 I/O Pins
- 74 bi-directional input/output pins, PCI-compliant for
5.0 volt and 3.3 volt buses for -1/-2/-3/-4 speed grades
- 8 high-drive input/distributed network pins
Eight Low-Skew Distributed Networks
- Two array clock/control networks available to the logic cell flip-flop
clock, set and reset inputs - each driven by an input-only pin
- Six global clock/control networks available to the logic cell F1, clock,
set and reset inputs and the input and I/O register clock, reset and enable
inputs as well as the output enable control - each driven by an input-only
or I/O pin, or any logic cell output or I/O cell feedback
High Performance
-
-
-
-
Input + logic cell + output total delays under 6 ns
Data path speeds over 400 MHz
Counter speeds over 300 MHz
FIFO speeds over 160 MHz
3-18
QL4009 Rev C.doc
QL4009
PINOUT DIAGRAM
84-PIN PLCC
QuickRAM
QL4009-1PL84C
3-19
QL4009 Rev C.doc
QL4009
PINOUT DIAGRAM
PIN # 76
PIN # 1
100-PIN TQFP
QuickRAM
QL4009-1PF100C
PIN # 51
PIN # 26
3-20
QL4009 Rev C.doc
QL4009
100 TQFP Pinout Table
100
100
100
100
Function
Function
Function
Function
TQFP
TQFP
TQFP
TQFP
1
I/O
26
TDI
51
I/O
76
TCK
2
I/O
27
I/O
52
I/O
77
STM
3
I/O
28
I/O
53
I/O
78
I/O
4
I/O
29
I/O
54
I/O
79
I/O
5
I/O
30
I/O
55
I/O
80
I/O
6
I/O
31
I/O
56
I/O
81
I/O
7
I/O
32
I/O
57
I/O
82
I/O
8
I/O
33
I/O
58
I/O
83
I/O
9
GND
34
I/O
59
GND
84
I/O
10
I/O
35
GND
60
I/O
85
GND
11
I
36
I/O
61
I
86
I/O
12
ACLK / I
37
I/O
62
ACLK / I
87
I/O
13
VCC
38
GND
63
VCC
88
GND
14
I
39
I/O
64
I
89
I/O
15
GCLK / I
40
I/O
65
GCLK / I
90
I/O
16
VCC
41
I/O
66
VCC
91
I/O
17
I/O
42
VCCIO
67
I/O
92
VCCIO
18
I/O
43
I/O
68
I/O
93
I/O
19
I/O
44
I/O
69
I/O
94
I/O
20
I/O
45
I/O
70
I/O
95
I/O
21
I/O
46
I/O
71
I/O
96
I/O
22
I/O
47
I/O
72
I/O
97
I/O
23
I/O
48
I/O
73
I/O
98
I/O
24
I/O
49
TRSTB
74
I/O
99
I/O
25
I/O
50
TMS
75
I/O
100
TDO
3-21
QL4009 Rev C.doc
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