QL58x2 Enhanced QuickPCI
Family Data Sheet
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33/66 MHz/32-bit PCI Master/Target with Embedded Programmable
Logic, Embedded Computational Units, and Dual Port SRAM
Device Highlights
High Performance PCI Controller
• 33/66 MHz 32-bit PCI Master/Target
• Zero-wait state PCI Master provides up to
264 MBps transfer rates
• Zero-wait-state PCI Target Write/One-wait-state
PCI Target Read interface
• Supports all PCI commands, including
configuration and MWI
• Supports fully-customizable byte enable for
master channels
• Target interface supports retry, disconnect
with/without data transfer, and target abort
• Fully programmable back-end interface
• Independent PCI bus (33/66 MHz) and local bus
(up to 160 MHz) clocks
• Fully customizable PCI Configuration Space
• Configurable FIFOs with depths up to 256 words
• Reference design with driver code
(Win 95/98/2000/NT 4.0) available
• PCI v2.3 compliant
• Supports Type 0 Configuration Cycles in Target
mode
• 3.3 V PCI signaling
• 1.8 V supply voltage
• 484-ball PBGA, 280-ball LFBGA, 208-pin
PQFP, 196-ball TFBGA, and 144-pin TQFP
packages
• Supports Extendable PCI functionality
• Unlimited/Continuous Burst Transfers supported
Extendable PCI Functionality
• Support for Configuration Space from
0
×
40 to 0
×
3FF
• PCI v2.3 Power Management Spec. compatible
• Multi-function, expanded capabilities, and
expansion ROM capable
• PCI v2.3 Vital Product Data (VPD) configuration
support
Flexible Programmable Logic
• Up to 1,348 logic cells
• Up to 50,688 RAM bits
• Up to 262 I/O pins
• All back-end interface and glue-logic can be
implemented on chip
• Six 32-bit busses interface between the PCI
Controller and the Programmable Logic
• Up to twenty-two 2,304 bit dual-port high
performance SRAM blocks
• Up to 3,482 flip-flops available
Figure 1: QL58x2 Block Diagram
PCI Bus 33 MHz/32-Bit Address and Data
Fixed
PCI Core
Parity
Check
Parity
Gen
Mux
Target
Control
Master
Control
Mux
FIFO
32-Bit Interface
DMA
Control
Configuration
Space
User
Defined
Registers
FIFO
FIFO
Programmable
Logic
XY User I/O for Flexible Local Bus
© 2004 QuickLogic Corporation
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QL58x2 Enhanced QuickPCI Family Data Sheet Rev. G
Architecture Overview
The QL58x2 device family of QuickPCI Embedded Standard Products (ESPs) provides a complete and
customizable PCI interface solution combined with programmable logic. Since the QL58x2 devices provide
optimized pre-verified PCI cores, the burden of PCI timing closure and PCI protocol compliance has been
eliminated and allows for the maximum 32-bit PCI bus bandwidth (264 MBps).
The programmable logic portion of this family contains up to 1,348 QuickLogic Logic Cells and up to 22
QuickLogic Dual-Port RAM Blocks. These configurable RAM blocks can be configured in many width/depth
combinations. They can also be combined with logic cells to form FIFOs, or be initialized via Serial EEPROM
on power-up and used as ROMs.
The QL58x2 device meets PCI 2.3 electrical and timing specifications and has been fully hardware-tested. The
QL58x2 device features 1.8 V operation with multi-volt compatible I/Os. The device can easily operate in 3 V
embedded systems and is fully compatible with 3.3 V applications.
PCI Controller
The PCI Controller is a 33/66 MHz 32-bit PCI 2.3 compliant Master/Target Controller capable of infinite
length Master Write and Read transactions at zero wait states (264 MBps).
The Master will never insert wait states during transfers, so data is supplied or received by FIFOs that can be
configured in the programmable region of the device. The Master is capable of initiating any type of PCI
commands, including configuration cycles and Memory Write and Invalidate (MWI). This enables the QL58x2
device family to act as a PCI host. The Master Controller will most often be operated by a DMA Controller in
the programmable region of the device. DMA Controller reference design is available and is included in the
QuickWorks
design software.
The Target interface offers full PCI Configuration Space and flexible target addressing. It supports zero-wait-
state target Write and one-wait-state target Read operations. It also supports retry, disconnect with/without
data transfer, and target abort requested by the back end. Any number of 32-bit BARs may be configured as
either memory or I/O space. All required and optional PCI 2.3 Configuration Space registers can be
implemented within the programmable region of the device. A reference design of a Target Configuration and
Addressing module is available and is included in the QuickWorks design software.
The interface ports are divided into a set of ports for master transactions and a set for target transactions. The
Master DMA controller and Target Configuration Space and Address Decoding are done in the programmable
logic region of the device. These functions are not timing critical, so leaving these elements in the
programmable region allows the greatest degree of flexibility to the designer. Reference DMA controller,
Configuration Space, and Address Decoding blocks are readily available so that the design cycle can be
minimized.
Table 1
shows several commonly implemented IP cores in the programmable logic portion of the
Master/Target Controller device. Their respective logic cell utilization and performance information are shown
clearly for easy reference. Notice that the Configuration Space/Address Decoding and DMA Controller IP
cores are labelled as essential IP cores. These IP blocks are necessary for the Master/Target Controller to be
fully functional. The optional IP cores are common interface IP cores made available so that designers may
implement according to their design requirements. These optional IP cores do not affect the functionality of
the Master/Target Controller.
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© 2004 QuickLogic Corporation
QL58x2 Enhanced QuickPCI Family Data Sheet Rev. G
Table 1: IP Implemented in Programmable Logic
Essential PCI IP Cores
Configuration Space/Address Decoding
Optional IP Cores
Async 32x32 FIFO
Async 128x32 FIFO
SDRAM Controller
DDR SDRAM Controller
Pulse Width Modulation
Logic Cells
110
Logic Cells
64
88
149
216
20
RAM
N/A
RAM
2
2
N/A
N/A
N/A
Performance
33/66 MHz
Performance
210 MHz
190 MHz
160 MHz
100 MHz
303 MHz
Configuration Space and Address Decode
The configuration space is completely customizable in the programmable region of the device.
PCI address and command decoding is performed by logic in the programmable section of the device. This
allows support for any size of memory or I/O space for back end logic. It also allows the user to implement
any subset of the PCI commands supported by the QL58x2. QuickLogic provides a reference Address
Register/Counter and Command Decode block.
DMA Master Target Controller
The customizable DMA controller included with the QuickWorks design software contains the following
features:
• Configurable DMA count size for Reads and Writes (up to 30-bits)
• Configurable DMA burst size for PCI (including unlimited/continuous burst)
• Customizable PCI command to use by core
• Customizable Byte Enable signal
• Programmable Arbitration between DMA Read & Write transactions
• DMA Registers may be mapped to any area of Target Memory Space, including:
Read Address (32-bit register)
Write Address (32-bit register)
Read Length (16-bit register) / Write Length (16-bit register)
Control and Status (32-bit register, includes 8 bit Burst Length)
• DMA Registers are available to the local design or the PCI bus
• Programmable Interrupt Control to signal end of transfer or other event
© 2004 QuickLogic Corporation
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QL58x2 Enhanced QuickPCI Family Data Sheet Rev. G
PCI Interface Symbol
Figure 2
shows the graphical interface symbol numbers you have to use in your schematic design in order to
attach the local interface programmable logic design to the PCI core. If you are designing with a top-level
Verilog or VHDL file you must use a structural instantiation of this PCI32V2 block instead of a graphical
symbol.
Figure 2: PCI Interface Symbol
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© 2004 QuickLogic Corporation
QL58x2 Enhanced QuickPCI Family Data Sheet Rev. G
PCI Master Interface
The internal signals used to interface with the PCI controller in the QL58x2 are listed in
Table 2
along with a
description of each signal. The direction of the signal indicates if the signal is an input provided by the local
interface (I) or an output provided by the PCI controller (O).
NOTE:
Signals that end with the character ‘N’ should be considered active-low (for example, Mst_IRDYN).
Table 2: PCI Master Interface
Signal
I/O
Description
PCI command to be used for the master transaction.
This signal must remain unchanged
throughout the period when Mst_Burst_Req is active. PCI commands considered as Reads
include Interrupt Acknowledge, I/O Read, Memory Read, Configuration Read, Memory
Read Multiple, and Memory Read Line. PCI commands considered as Writes include
Special Cycle, I/O Write, Memory Write, Configuration Write, Memory Write, and
Invalidate.Users should make sure that only valid PCI commands are supplied.
Request use of the PCI bus.
When it is active, the core requests the PCI bus and then
generates a Master transaction. This signal should be held active until all requested data is
transferred on the PCI bus and deactivated in the 2nd clock cycle following the last data
transfer on PCI (to avoid being considered as requesting a new transaction).
Address for master DMA writes.
This address must be treated as valid from the beginning
of a DMA Write until the DMA Write operation is complete. It should be incremented by four
bytes each time data is transferred on the PCI bus.
Address for master DMA reads.
This address must be treated as valid from the beginning
of a DMA read until the DMA Read operation is complete. It should be incremented by four
bytes each time data is transferred on the PCI bus.
Data for master DMA Writes (to PCI bus).
Byte enables for master DMA Reads and writes.
Active-low.
Data and byte enable valid on Mst_WrData[31:0] (for master Write only) and
Mst_BE[3:0] (for both master Read and Write).
Data receive acknowledge for Mst_WrData[31:0] (for master Write only) and
Mst_BE[3:0] (for both).This
serves as the PUSH control for the internal FIFO and the POP
control for the external FIFO (in FPGA region) which provides data and byte enables to the
PCI32 core.
Byte enable select for master transactions.
When low, Mst_BE[3:0] should remain
constant throughout the entire transfer (when Mst_Burst_Req is active) and it is used for
every data phase of the master transaction. When high, Mst_BE[3:0] pushed into internal
FIFO (along with data in case of master Write) is used. Should be held constant throughout
the transaction.
Master Write transaction is completed.
Active for only one clock cycle.
Master Read termination mode select when Mst_BE_Sel is high.
When both
Mst_BE_Sel and Mst_Rd_Term_Sel are high, Master Read termination happens when the
internal FIFO is empty, and Mst_Two_Reads and Mst_One_Read are ignored. When either
signal is low, Mst_Two_Reads and Mst_One_Read are used to signal the end of Master
Read. Should be held constant throughout the transaction.
Signals to the PCI32 core that only one data transfer remains to be read in the burst Read.
Two data transfers remain to be read in the burst Read
It is not used for single-data-
phase Master Read transactions.
Master Read data valid on Usr_Addr_WrData[31:0].
This serves as the PUSH control for
the external FIFO (in FPGA region) that receives data from the PCI32 core.
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PCI_cmd[3:0]
I
Mst_Burst_Req
I
Mst_WrAd[31:0]
I
Mst_RdAd[31:0]
Mst_WrData[31:0]
Mst_BE[3:0]
Mst_WrData_Valid
I
I
I
I
Mst_WrData_Rdy
O
Mst_BE_Sel
I
Mst_WrBurst_Done
O
Mst_Rd_Term_Sel
I
Mst_One_Read
Mst_Two_Reads
Mst_RdData_Valid
I
I
O
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