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Eclipse Family Data Sheet

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Combining Performance, Density, and Embedded RAM

Device Highlights

Flexible Programmable Logic

• 0.25 µ, 5 layer metal CMOS process

• 2.5 V Vcc, 2.5/3.3 V dive capable I/O

• Up to 4032 logic cells

• Up to 583,000 max system gates

• Up to 347 I/O

Programmable I/O

• High performance: <3.2 ns Tco

• Programmable slew rate control

• Programmable I/O standards:

LVTTL, LVCMOS, PCI, GTL+, SSTL2,

and SSTL3

Eight independent I/O banks

Three register configurations: input, output and

output enable

Embedded Dual Port SRAM

• Up to thirty-six 2,304-bit dual port SRAM blocks

• Up to 82,900 RAM bits

• RAM/ROM/FIFO Wizard for automatic

configuration

• Configurable and cascadable

Advanced Clock Network

• Nine global clock networks

One dedicated

Eight programmable

• Sixteen I/O (high-drive) networks

• Twenty quad-net networks: five per quadrant

Figure 1: Eclipse Block Diagram

Applications

• Signal processing operators

• Signal processing functions

• Networking/communications for VoIP

• Speech/voice processing

• Channel coding

PLL

Embedded RAM Blocks

PLL

Fabric

PLL

Embedded RAM Blocks

PLL

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Eclipse Family Data Sheet Rev. F

Table 1: Eclipse Product Family Members

QL6250

Max Gates

Logic Array

Logic Cells

Max Flip-Flops

Max I/O

RAM Modules

RAM bits

PQFP

Packages

PBGA (1.27 mm)

FPBGA (1.0 mm)

LFBGA (0.8 mm)

248,160

40x24

960

2,670

250

46,100

208

484

280

QL6325

320,640

48x32

1,536

4,002

310

55,300

208

484

280

QL6500

488,064

64x48

3,072

7,185

347

73,700

516

484

280

QL6600

583,008

72x56

4,032

9,105

347

82,900

516

484

280

Table 2: Max I/O per Device /Package Combination

Device

QL6250

QL6325

QL6500

QL6600

208 PQFP

280 FPBGA

163

484 PBGA

250

310

327

516 PBGA

347

QuickWorks Design Software

The QuickWorks

package provides the most complete ESP and FPGA software solution from design entry

to logic synthesis, to place and route to simulation. The packages provide a solution for designers who use

third party tools from Cadence, Mentor, OrCAD, Synopsys, Viewlogic and other third-party tools for design

entry, synthesis, or simulation.

Process Data

Eclipse is fabricated on a 0.25

μm

five-layer metal CMOS process. The core voltage is 2.5 V V

supply and

3.3 V tolerant I/O with the addition of 3.3 V V

CCIO

. Eclipse is available in commercial, industrial, and military

temperature grades.

Programmable Logic Architectural Overview

The Eclipse logic cell structure is presented in

Figure 2.

This architectural feature addresses current register-

intensive designs.

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Eclipse Family Data Sheet Rev. F

Figure 2: Eclipse Logic Cell

Q2Z

Table 3: Performance Standards

Function

Multiplexer

Parity Tree

Counter

Description

16:1

16 bit

32 bit

128 x 32

FIFO

Clock to Out

System

clock

256 x 16

128 x 64

Slowest Speed Grade

5 ns

6 ns

250 MHz

155 MHz

4.5 ns

200 MHz

Fastest Speed Grade

2.8 ns

3.4 ns

450 MHz

280 MHz

2.5 ns

400 MHz

The second register has a two-to-one multiplexer controlling its input. The register can be loaded from the NZ

output or directly from a dedicated input.

NOTE:

The input “PP” is not an “input” in the classical sense. It can only be tied high or low using default

links only and is used to select which path “NZ” or “PS” is used as an input to the register. All other inputs

can be connected not only to “tiehi” and “tielo” but to multiple routing channels as well.

The complete logic cell consists of 2 six-input AND gates, 4 two-input AND gates, 7 two-to-one multiplexers,

and 2 D flip-flop with asynchronous SET and RESET controls. The cell has a fan-in of 30 (including register

control lines) and fits a wide range of functions with up to 17 simultaneous inputs. It has 6 outputs;

4 combinatorial and 2 registered. The high logic capacity and fan-in of the logic cell accommodate many user

functions with a single level of logic delay while other architectures require two or more levels of delay.

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Eclipse Family Data Sheet Rev. F

RAM Modules

The Eclipse Family includes multiple dual-port 2,304-bit RAM modules for implementing RAM, ROM and

FIFO functions. Each module is user-configurable into four different block organizations. Modules can also be

cascaded horizontally to increase their effective width or vertically to increase their effective depth as shown

Figure 3.

The RAM can also be configured as a modified Harvard Architecture, similar to those found in

DSPs.

Figure 3: 2,304-bit Eclipse RAM Module

MODE[1:0]

WA[9:0]

WD[17:0]

WCLK

ASYNCRD

RA[9:0]

RD[17:0]

RCLK

The number of RAM modules varies from 20 to 36 blocks within the Eclipse family, for a total of 46.1 to 82.9

K bits of RAM. Using two “mode” pins, designers can configure each module into 128 x 18 (Mode 0), 256 x

9 (Mode 1), 512 x 4 (Mode 2), or 1024 x 2 blocks (Mode 3). The blocks are also easily cascadable to increase

their effective width and/or depth. See

Figure 4.

Figure 4: Cascaded RAM Modules

WDATA

WADDR

RAM

Module

(2,304 bits)

RDATA

RADDR

WDATA

RAM

Module

(2,304 bits)

RDATA

The RAM modules are dual-port, with completely independent READ and WRITE ports and separate READ

and WRITE clocks. The READ ports support asynchronous and synchronous operation, while the WRITE

ports support synchronous operation. Each port has 18 data lines and 10 address lines, allowing word lengths

of up to 18 bits and address spaces of up to 1024 words. Depending on the mode selected, however, some

higher order data or address lines may not be used.

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Eclipse Family Data Sheet Rev. F

The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read Enable (RE) acts

as a clock enable for synchronous READ operation (ASYNCRD input low), or as a flow-through enable for

asynchronous READ operation (ASYNCRD input high).

Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by

connecting corresponding address lines together and dividing the words between modules.

A similar technique can be used to create depths greater than 512 words. In this case address signals higher

than the ninth bit are encoded onto the write enable (WE) input for WRITE operations. The READ data outputs

are multiplexed together using encoded higher READ address bits for the multiplexer SELECT signals.

The RAM blocks can be loaded with data generated internally (typically for RAM or FIFO functions) or with

data from an external PROM (typically for ROM functions).

Phase Locked Loops (PLLs)

Instead of requiring extra components, designers simply need to instantiate one of the pre-configured models

described in this section and listed in

Table 4.

The QuickLogic built-in PLLs support a wider range of

frequencies than many other PLLs. Also, QuickLogic PLLs can be cascaded to support different ranges of

frequency multiplications or divisions, driving the device at a faster or slower rate than the incoming clock

frequency. Most importantly, they achieve a very short clock-to-out time—generally less than 3 ns. This low

clock-to-out time is achieved by the PLL subtracting the clock tree delay through the feedback path, effectively

making the clock tree delay zero.

Figure 5

illustrates a typical QuickLogic ESP PLL.

Figure 5: PLL Block

1st Quadrant

2nd Quadrant

3rd Quadrant

Frequency Divide

Filter

vco

PLL Bypass

4th Quadrant

Clock

Tree

FIN

Frequency Multiply

FOUT

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