QL6500 Eclipse Data Sheet
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Combining Performance, Density and Embedded RAM
Device Highlights
Flexible Programmable Logic
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.25
µ
m, Five layer metal CMOS Process
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2.5 V V
CC
, 2.5 V/3.3 V Drive Capable I/O
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3,032 Logic Cells
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488,064 Max System Gates
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Up to 444 I/O Pins
Advanced Clock Network
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Nine Global Clock Networks:
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One Dedicated
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Eight Programmable
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20 Quad-Net Networks: Five per Quadrant
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16 I/O Controls: Two per I/O Bank
Embedded Dual Port SRAM
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Thirty six 2,304-bit Dual Port High
Memory - Dual Port RAM
High Speed Logic Cells
488K Gates
Performance SRAM Blocks
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82,900 RAM Bits
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RAM/ROM/FIFO Wizard for Automatic
Configuration
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Configurable and Cascadable
Memory - Dual Port RAM
Programmable I/O
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High performance Enhanced I/O (EIO):
Figure 1: Eclipse Block Diagram
Less than 3 ns Tco
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Programmable Slew Rate Control
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Programmable I/O Standards:
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LVTTL, LVCMOS, PCI, GTL+, SSTL2,
and SSTL3
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Eight Independent I/O Banks
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Three Register Configurations: Input,
Output, and Output Enable
© 2002 QuickLogic Corporation
www.quicklogic.com
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QL6500 Eclipse Data Sheet Rev C
Electrical Specifications
AC Characteristics at V
CC
= 2.5 V, TA = 25° C (K = 0.74)
The AC Specifications are provided from
Table 1
to
Table 10
. Logic Cell diagrams and
waveforms are provided from
Figure 2
to
Figure 15
.
Figure 2: Eclipse Logic Cell
Table 1: Logic Cells
Symbol
Logic Cells
t
PD
t
SU
t
HL
t
CO
t
CWHI
t
CWLO
t
SET
t
RESET
t
SW
t
RW
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Combinatorial Delay of the longest path: time taken by the combinatorial circuit to
output
Setup time: time the synchronous input of the flip-flop must be stable before the
active clock edge
Hold time: time the synchronous input of the flip-flop must be stable after the active
clock edge
Clock to out delay: the amount of time taken by the flip-flop to output after the
active clock edge.
Clock High Time: required minimum time the clock stays high
Clock Low Time: required minimum time that the clock stays low
Set Delay: time between when the flip-flop is ”set” (high)
and when the output is consequently “set” (high)
Reset Delay: time between when the flip-flop is ”reset” (low) and when the output
is consequently “reset” (low)
Set Width: time that the SET signal remains high/low
Reset Width: time that the RESET signal remains high/low
Parameter
Value (ns)
Min
-
0.22
0
-
0.46
0.46
-
-
0.3
0.3
Max
0.257
-
-
0.255
-
-
0.18
0.09
-
-
2
© 2002 QuickLogic Corporation
QL6500 Eclipse Data Sheet Rev C
SET
D
CLK
RESET
Q
Figure 3: Logic Cell Flip Flop
CLK
t
CWHI
(min)
t
CWLO
(min)
SET
RESET
Q
t
RESET
t
RW
t
SET
t
SW
Figure 4: Logic Cell Flip Flop Timings - First Waveform
CLK
D
t
SU
t
HL
Q
t
CO
Figure 5: Logic Cell Flip Flop Timings - Second Waveform
© 2002 QuickLogic Corporation
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QL6500 Eclipse Data Sheet Rev C
Quad net
Figure 6: Eclipse Global Clock Structure
Table 2: Eclipse Clock Performance
Clock
Parameters
Clock Performance
Global
Logic Cells (Internal)
I/O’s (External)
Clock signal generated internally
Clock signal generated externally
1.51 ns (max)
2.06 ns (max)
Dedicated
1.59 ns (max)
1.73 ns (max)
Table 3: Eclipse Global Clock Performance
Clock Segment
Parameter
Min
t
PGCK
t
BGCK
Global clock pin delay to quad net
Global clock buffer delay
(quad net to flip flop)
-
-
Value (ns)
Max
1.34
0.56
Programmable Clock
External Clock
Global Clock Buffer
Global Clock
Clock
Select
t
PGCK
t
BGCK
Figure 7: Global Clock Structure Schematic
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© 2002 QuickLogic Corporation
QL6500 Eclipse Data Sheet Rev C
[9:0]
[17:0]
WA
WD
WE
WCLK
RE
RCLK
RA
RD
ASYNCRD
RAM Module
[9:0]
[17:0]
Figure 8: RAM Module
Table 4: RAM Cell Synchronous Write Timing
Symbol
RAM Cell Synchronous Write Timing
t
SWA
t
HWA
t
SWD
t
HWD
t
SWE
t
HWE
t
WCRD
WA setup time to WCLK: time the WRITE ADDRESS must be stable before the
active edge of the WRITE CLOCK
WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active
edge of the WRITE CLOCK
WD setup time to WCLK: time the WRITE DATA must be stable before the active
edge of the WRITE CLOCK
WD hold time to WCLK: time the WRITE DATA must be stable after the active edge
of the WRITE CLOCK
WE setup time to WCLK: time the WRITE ENABLE must be stable before the active
edge of the WRITE CLOCK
WE hold time to WCLK: time the WRITE ENABLE must be stable after the active
edge of the WRITE CLOCK
WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the
time when the data is available at RD
Parameter
Value (ns)
Min
0.675
0
0.654
0
0.623
0
-
Max
-
-
-
-
-
-
4.38
© 2002 QuickLogic Corporation
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www.quicklogic.com
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