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six layer metal CMOS process
1.8 V Vcc, 1.8/2.5/3.3 V drive capable I/O
Up to 4,008 dedicated flip-flops
Up to 55.3 K embedded RAM Bits
Up to 313 I/O
Up to 370 K system gates
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Multiple dedicated Low Skew Clock
Networks
High drive input-only networks
Quadrant-based segmentable clock networks
User Programmable Phase Locked Loops
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Hardwired DSP building blocks with integrated
Multiply, Add, and Accumulate Functions.
Compliant
Low Power Capability
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ViaLink technology that protects intellectual
property from design theft and reverse
engineering. No external configuration memory
needed; Instant-on at Power-up.
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Up to twenty-four 2,304 bit Dual Port High
Performance SRAM Blocks
Up to 55,296 embedded RAM bits
RAM/ROM/FIFO Wizard for automatic
configuration
Configurable and cascadable
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Programmable Slew Rate Control
Programmable I/O Standards:
LVTTL, LVCMOS, LVCMOS18, PCI,
PLL
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Embeded Computational Units
PLL
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Fabric
supporting multiple standards in one device
I/O Register Configurations: Input,
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The QuickWorks
package provides the most complete ESP and FPGA software solution from
design entry to logic synthesis, to place and route, and simulation. The package provides a
solution for designers who use third party tools from Cadence, Mentor, OrCAD, Synopsys,
Viewlogic, and other third-party tools for design entry, synthesis, or simulation.
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µ
, six layer metal CMOS process. The core voltage is
1.8 V Vcc supply and the I/Os are up to 3.3 V tolerant. The Eclipse-II product line is available in
commercial, industrial, and military temperature grades.
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The Eclipse-II logic cell structure is presented in
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today's register-intensive designs.
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256 x 16
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6 ns
6 ns
250 MHz
250 MHz
155 MHz
155 MHz
155 MHz
4.5 ns
200 MHz
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2.8 ns
3.4 ns
3.4 ns
450 MHz
450 MHz
280 MHz
280 MHz
280 MHz
2.5 ns
400 MHz
The Eclipse-II logic cell structure presented in
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is a dual register, multiplexor-based logic
cell. It is designed for wide fan-in and multiple, simultaneous output funtions. Both registers share
CLK, SET, and RESET inputs. The second register has a two-to-one multiplexer controlling its
input. The register can be loaded from the NZ output or directly from a dedicated input.
NOTE:
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The complete logic cell consists of two 6-input AND gates, four two-input AND gates, seven two-
to-one multiplexers, and two D flip-flops with asynchronous SET and RESET controls. The cell
has a fan-in of 30 (including register control lines), fits a wide range of functions with up to 17
simultaneous inputs, and has six outputs (four combinatorial and two registered). The high logic
capacity and fan-in of the logic cell accommodates many user functions with a single level of logic
delay while other architectures require two or more levels of delay.
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A4
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B2
C1
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D2
E1
E2
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The Eclipse-II Product Family includes up to 24 dual-port 2,304-bit RAM modules for
implementing RAM, ROM, and FIFO functions. Each module is user-configurable into four
different block organizations and can be cascaded horizontally to increase their effective width, or
vertically to increase their effective depth as shown in
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.
2,304-bit RAM Module
MODE[1:0]
WA[9:0]
WD[17:0]
WE
WCLK
ASYNCRD
RA[9:0]
RD[17:0]
RE
RCLK
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The number of RAM modules varies from 4 to 24 blocks for a total of 9.2 K to 55.3 K bits of
RAM. Using two "mode" pins, designers can configure each module into 128 x 18 (Mode 0), 256
x 9 (Mode 1), 512 x 4 (Mode 2), or 1024 x 2 blocks (Mode 3). The blocks are also easily
cascadable to increase their effective width and/or depth (see
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WDATA
WADDR
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(2,304 bits)
RDATA
RADDR
WDATA
RAM
Module
(2,304 bits)
RDATA
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The RAM modules are dual-port, with completely independent READ and WRITE ports and
separate READ and WRITE clocks. The READ ports support asynchronous and synchronous
operation, while the WRITE ports support synchronous operation. Each port has 18 data lines
and 10 address lines, allowing word lengths of up to 18 bits and address spaces of up to 1,024
words. Depending on the mode selected, however, some higher order data or address lines may
not be used.
The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read
Enable (RE) acts as a clock enable for synchronous READ operation (ASYNCRD input low), or as
a flow-through enable for asynchronous READ operation (ASYNCRD input high).
Designers can cascade multiple RAM modules to increase the depth or width allowed in single
modules by connecting corresponding address lines together and dividing the words between
modules.
A similar technique can be used to create depths greater than 512 words. In this case address
signals higher than the ninth bit are encoded onto the write enable (WE) input for WRITE
operations. The READ data outputs are multiplexed together using encoded higher READ
address bits for the multiplexer SELECT signals.
The RAM blocks can be loaded with data generated internally (typically for RAM or FIFO
functions) or with data from an external PROM (typically for ROM functions).
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Traditional Programmable Logic architectures do not implement arithmetic functions efficiently
or effectively—these functions require high logic cell usage while garnering only moderate
performance results.
The Eclipse-II architecture allows for functionality above and beyond that achievable using
programmable logic devices. By embedding a dynamically reconfigurable computational unit, the
Eclipse-II device can address various arithmetic functions efficiently. This approach offers greater
performance than traditional programmable logic implementations. The embedded block is
implemented at the transistor level as shown in
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