QuickLogic PolarPro
®
Device Data Sheet — QL1P075,
QL1P100, QL1P200, and QL1P300
••••••
Combining Low Power, Performance, Density, and Embedded RAM
• Quadrant-based segmentable clock networks
Device Highlights
Low Power Programmable Logic
• As low as 2.2 µA
• 0.18 µm, six layer metal CMOS process
• 1.8 V core voltage, 1.8/2.5/3.3 V drive
capable I/Os
• Up to 55 kilobits of SRAM
• Up to 238 I/Os available
• Up to 300,000 system gates
• Nonvolatile, instant-on
• IEEE 1149.1 boundary scan testing compliant
20 quad clock networks per device
4 quad clock networks per quadrant
1 dedicated clock network per quadrant
• Two user Configurable Clock Managers (CCMs)
Very Low Power (VLP) Mode
• QuickLogic PolarPro has a special VLP pin
which can enable a low power sleep mode that
significantly reduces the overall power
consumption of the device by placing the device in
standby
• Enter VLP mode from normal operation in less
than 250 µs (typical)
• Exit from VLP mode to normal operation in less
than 250 µs (typical)
Embedded Dual-Port SRAM
• Up to twelve dual-port 4-kilobit high performance
SRAM blocks
• True dual-port capability
• Embedded synchronous/asynchronous FIFO
controller
• Configurable and cascadable aspect ratio
Security Links
There are several security links to disable JTAG
access to the device. Programming these optional
links completely disables access to the device from
the outside world and provides an extra level of
design security not possible in SRAM-based FPGAs.
Figure 1: QuickLogic PolarPro Block Diagram
DDR/GPIO
DDR/GPIO
DDR/GPIO
DDR/GPIO
Programmable I/O
• Bank programmable drive strength
GPIO
CCM
GPIO
• Bank programmable slew rate control
• Independent I/O banks capable of supporting
multiple I/O standards in one device
• Native support for DDR I/Os
• Bank programmable I/O standards: LVTTL,
LVCMOS, LVCMOS18, PCI, SSTL2, SSTL3 and
SSDL18
Embedded RAM Blocks
FIFO Controller
GPIO
Fabric
GPIO
GPIO
GPIO
• Multiple low skew clock networks
GPIO
Embedded RAM Blocks
GPIO
GPIO
GPIO
1 dedicated global clock network
4 programmable global clock networks
•
•
•
•
© 2009 QuickLogic Corporation
www.quicklogic.com
•
•
GPIO
Advanced Clock Network
FIFO Controller
GPIO
1
QuickLogic PolarPro
®
Device Data Sheet — QL1P075, QL1P100, QL1P200, and QL1P300 Rev. D
Ultra-Low Power FPGA Combining Performance, Density, and
Embedded RAM
Table 1: PolarPro QL1P075, QL1P100, QL1P200, and QL1P300 Devices
Features
Max Gates
Logic Cells
Max I/O
RAM Modules
FIFO Controllers
RAM bits
CCMs
WLCSP (0.5 mm)
TFBGA (0.5 mm)
Packages
TFBGA (0.5 mm)
TQFP (0.5 mm)
TFBGA (0.8 mm)
LBGA (1.0 mm)
QL1P075
75,000
512
168
8
8
36,864
2
a
99
-
132
144
196
256
QL1P100
100,000
640
184
8
8
36,864
2
a
-
121
132
144
196
256
QL1P200
200,000
1,536
238
12
12
55,296
2
-
-
132
-
-
256, 324
QL1P300
300,000
1,920
238
12
12
55,296
2
-
-
132
-
-
256, 324
a. The PolarPro 144-pin TQFP and 132-pin TFBGA devices have one CCM. The PolarPro 99-pin
WLCSP, 196-pin TFBGA, 256-pin LBGA and 324-pin LBGA devices have two CCMs.
Table 2: Maximum Usable I/Os
Device
QL1P075
QL1P100
QL1P200
QL1P300
99 WLCSP
-
-
-
63
121 TFBGA
132 TFBGA
144 TQFP
196 TFBGA
256 LBGA
(6 mm x 6mm) (8 mm x 8 mm) (20 mm x 20 mm) (12 mm x 12 mm) (17 mm x 17 mm)
-
76
-
-
77
77
74
74
97
97
-
-
136
136
-
-
168
184
184
184
Process Data
The QuickLogic PolarPro is fabricated on a 0.18µ, six layer metal CMOS process. The core voltage is 1.8 V.
The I/O voltage input tolerance and output drive can be set as 1.8 V, 2.5 V, and 3.3 V.
•
2
•
www.quicklogic.com
•
•
•
•
© 2009 QuickLogic Corporation
QuickLogic PolarPro
®
Device Data Sheet — QL1P075, QL1P100, QL1P200, and QL1P300 Rev. D
Programmable Logic Architectural Overview
The QuickLogic PolarPro logic cell structure presented in
Figure 2
is a single register, multiplexer-based logic
cell. It is designed for wide fan-in and multiple, simultaneous output functions. The cell has a high fan-in, fits
a wide range of functions with up to 24 simultaneous inputs (including register control lines), and four outputs
(three combinatorial and one registered). The high logic capacity and fan-in of the logic cell accommodates
many user functions with a single level of logic delay.
The QuickLogic PolarPro logic cell can implement:
• Two independent 3-input functions
• Any 4-input function
• 8 to 1 mux function
• Independent 2 to 1 mux function
• Single dedicated register with clock enable, active high set and reset signals
• Direct input selection to the register, which allows combinatorial and register logic to be used separately
• Combinatorial logic that can also be configured as an edge-triggered master-slave D flip-flop
Figure 2: PolarPro Logic Cell
QST
QDS
TBS
TAB
TSL
TI
TA1
TA2
TB1
TB2
BAB
BSL
BI
BA1
BA2
BB1
BB2
FS
F1
F2
QDI
QEN
QCK
QRT
TZ
0
1
0
1
0
1
0
1
0
1
CZ
S
D
E
Q
QZ
0
1
0
1
0
1
R
0
1
FZ
© 2009 QuickLogic Corporation
www.quicklogic.com
•
•
•
•
•
•
3
QuickLogic PolarPro
®
Device Data Sheet — QL1P075, QL1P100, QL1P200, and QL1P300 Rev. D
RAM Modules
The PolarPro QL1P075, QL1P100, QL1P200, and QL1P300 devices have 4-kilobit (4,608 bits) RAM
blocks.
The RAM features include:
• Independently configurable read and write data bus widths
• Independent read and write clocks
• Horizontal and vertical concatenation
• Write byte enables
• Selectable pipelined or non-pipelined read data
Figure 3: 4-Kilobit Dual-Port RAM Block
WD[17:0]
WA[8:0]
WEN[1:0]
WD_SEL
WCLK
RA[8:0]
RD_SEL
RCLK
RD[17:0]
Table 3: RAM Interface Signals
Signal Name
Inputs
WD [17:0]
WA [8:0]
WEN [1:0]
WD_SEL
WCLK
RA [8:0]
RD_SEL
RCLK
RD [17:0]
Write Data
Write Address
Write Enable (two 9-bit enables)
Write Chip Select
Write Clock
Read Address
Read Chip Select
Read Clock
Output
Read Data
Function
The read and write data buses of a RAM block can be arranged to variable bus widths. The bus widths can be
configured using the RAM Wizard available in QuickWorks, QuickLogic’s development software. The selection
of the RAM depth and width determines how the data is addressed.
•
4
•
www.quicklogic.com
•
•
•
•
© 2009 QuickLogic Corporation
QuickLogic PolarPro
®
Device Data Sheet — QL1P075, QL1P100, QL1P200, and QL1P300 Rev. D
The RAM blocks also support data concatenation. Designers can cascade multiple RAM modules to increase
the depth or width by connecting corresponding address lines together and dividing the words between
modules. Generally, this requires the use of additional programmable logic resources. However, when
concatenating only two 4-kilobit RAM blocks, they can be concatenated horizontally or vertically without using
any additional programmable fabric resources.
For example, two internal 4-kilobit dual-port RAM blocks can be concatenated vertically to create a 512x18
RAM block or horizontally to create a 256x36 RAM block. A block diagram of horizontal and vertical
concatenation is displayed in
Figure 4.
Figure 4: Horizontal and Vertical Concatenation Examples
256x36 Dual-Port RAM
512x18 Dual-Port RAM
WD[35:0]
WA[8:0]
WEN[3:0]
WD_SEL
WCLK
RA[8:0]
RD_SEL
RCLK
RD[35:0]
WD[17:0]
WA[8:0]
WEN[1:0]
WD_SEL
WCLK
RA[8:0]
RD_SEL
RCLK
RD[17:0]
Horizontal Concatenation
Vertical Concatenation
Table 4
shows the various RAM configurations supported by the PolarPro RAM modules.
Table 5: Available Dual-Port RAM Configurations
Device
Number of
RAM Blocks
1
QL1P075
QL1P100
QL1P200
QL1P300
1
2
2
2
Depth
256
512
256
512
1024
Width
1-18
1-9
1-36
1-18
1-9
True Dual-Port RAM
PolarPro dual-port RAM modules can also be concatenated to generate true dual-port RAMs. The true dual-
port RAM module’s Port1 and Port2 have completely independent read and write ports, and separate read
and write clocks. This allows Port1 and Port2 to have different data widths and clock domains. It is important
to note that there is no circuitry preventing a write and read operation to the same address space at the same
time. Therefore, it is up to the designer to ensure that the same address is not read from and written to
© 2009 QuickLogic Corporation
www.quicklogic.com
•
•
•
•
•
•
5
嵌入式系统
