and mainframe systems. Several can be used in parallel or scattered
throughout a system for guaranteed low skew, system-wide clock distribu-
tion networks.
For more information on PLL clock driver products, see Application Note
AN-227.
FUNCTIONAL BLOCK DIAGRAM
REF_SEL
LO CK
SYNC
0
SYNC
1
O E/RST
0
0
1
PH A S E
D ETEC TO R
LO O P
FIL TER
1
PE
FEE DBACK
PLL_E N
FREQ _SEL
VCO
1
/2
0
R
D
R
D
R
D
R
D
R
D
R
D
R
D
Q
Q
Q
Q
Q
Q
Q
Q
Q /2
Q
5
Q
4
Q
3
Q
2
Q
1
Q
0
2xQ
INDUSTRIAL TEMPERATURE RANGE
1
c
2000
Integrated Device Technology, Inc.
SEPTEMBER 2000
DSC-5815/-
QS5919T
LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
GND
Q
5
V
DD
OE/RST
FEEDBACK
REF_SEL
SYNC
0
AV
DD
PE
AGND
SYNC
1
FREQ_SEL
GND
Q
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SO28-9
21
20
19
18
17
16
15
28
27
26
25
24
23
22
Q
4
V
DD
2xQ
Q/2
GND
Q
3
V
DD
Q
2
GND
AGND
FEEDBACK
REF_SEL
SYNC
0
AV
D D
PE
5
6
7
8
9
10
11
12
13
14
15
16
17
18
J28-1
OE/RST
GND
4
3
2
1
28
Q
4
27
26
25
24
23
22
21
20
19
Q/2
GND
Q
3
V
DD
Q
2
GND
LOCK
LOCK
PLL_EN
GND
Q
1
V
DD
FREQ_SEL
SYNC
1
GND
GND
V
DD
Q
1
QSOP
TOP VIEW
PLCC
TOP VIEW
(1)
Unit
V
V
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DD
, AV
DD
V
IN
Rating
Supply Voltage to Ground
DC Input Voltage V
IN
Maximum Power
QSOP
Dissipation (T
A
= 85°C)
PLCC
Storage Temperature Range
Max.
–0.5 to +7
–0.5 to +7
T
STG
655
mW
770
mW
–65°C to +150°C °C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
CAPACITANCE
(T
A
= 25° C, f = 1MHz, V
IN
= 0V)
QSOP
Parameter
C
IN
Typ.
3
Max.
4
Typ.
4
PLCC
Max.
6
Unit
pF
2
PLL_EN
Q
0
2xQ
V
DD
Q
5
V
DD
QS5919T
LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Name
SYNC
0
SYNC
1
REF_SEL
FREQ_SEL
FEEDBACK
Q
0
-Q
4
Q
5
2xQ
Q/2
LOCK
OE/RST
PLL_EN
PE
V
DD
AV
DD
GND
AGND
I/O
I
I
I
I
I
O
O
O
O
O
I
I
I
—
—
—
—
Reference clock input
Reference clock input
Reference clock select. When 1, selects SYNC
1
. When 0, selects SYNC
0
.
VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency.
PLL feedback input which is connected to a user selected output pin. External feedback provides flexibility for different output
frequency relationships. See the Frequency Selection Table for more information.
Clock outputs
Clock output. Matched in frequency, but inverted with respect to Q.
Clock output. Matched in phase, but frequency is double the Q frequency.
Clock output. Matched in phase, but frequency is half the Q frequency.
PLL lock indication signal. 1 indicates positive lock. 0 indicates that the PLL is not locked and outputs may not be synchronized to
the inputs.
Output enable/asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1,
outputs are enabled.
PLL enable. Enables and disables the PLL. Useful for testing purposes.
When
PE
is LOW, outputs are synchronized with the positive edge of SYNC. When HIGH, outputs are synchronized with the
negative edge of SYNC.
Power supply for output buffers.
Power supply for phase lock loop and other internal circuitries.
Ground supply for output buffers.
Ground supply for phase lock loop and other internal circuitries.
Description
OUTPUT FREQUENCY SPECIFICATIONS
Industrial: T
A
= –40°C to +85°C, AV
DD
/
V
DD
= 5.0V ± 10%
Symbol
F
MAX_2XQ
F
MAX_Q
F
MAX_Q/2
F
MIN_2XQ
F
MIN_Q
F
MIN_Q/2
Description
Max Frequency, 2xQ
Max Frequency, Q
0
- Q
4
, Q
5
Max Frequency, Q/2
Min Frequency, 2xQ
Min Frequency, Q
0
- Q
4
, Q
5
Min Frequency, Q/
2
– 55
55
27.5
13.75
20
10
5
– 70
70
35
17.5
20
10
5
– 100
100
50
25
20
10
5
– 133
133
66.5
33.25
20
10
5
– 160
160
80
40
20
10
5
Units
MHz
MHz
MHz
MHz
MHz
MHz
3
QS5919T
LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
FREQUENCY SELECTION TABLE
FREQ_SEL
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
Output Used for
Feedback
Q/
2
Q
0
-Q
4
Q
5
2xQ
Q/2
Q
0
-Q
4
Q
5
2xQ
SYNC (MHz)
(allowable range)
(1)
Min.
Max
F
MIN_Q/2
F
MIN_Q
F
MIN_Q
F
MIN_2XQ
F
MIN_Q/2
/2
F
MIN_Q
/2
F
MIN_Q
/2
F
MIN_2XQ
/2
F
MAX _Q/2
F
MAX _Q
F
MAX _Q
F
MAX _2XQ
F
MAX _Q/2
/2
F
MAX _Q
/2
F
MAX _Q
/2
F
MAX _2XQ
/2
Q/
2
SYNC
SYNC / 2
– SYNC / 2
SYNC / 4
SYNC
SYNC / 2
– SYNC / 2
SYNC / 4
Output Frequency Relationships
(2)
Q
5
Q
0
- Q
4
– SYNC X 2
– SYNC
SYNC
– SYNC / 2
– SYNC X 2
– SYNC
SYNC
– SYNC / 2
SYNC X 2
SYNC
– SYNC
SYNC / 2
SYNC X 2
SYNC
– SYNC
SYNC / 2
2XQ
SYNC X 4
SYNC X 2
– SYNC X 2
SYNC
SYNC X 4
SYNC X 2
– SYNC X 2
SYNC
NOTES:
1. Operation in the specified SYNC frequency range guarantees that the VCO will operate in its optimal range of 20MHz to F
MAX_2
X
Q
. Operation with
Sync inputs outside specified frequency ranges may result in out-of-lock outputs. FREQ_SEL only affects VCO frequency and does not affect
output frequencies.
2. The lock output pin (LOCK) may not indicate reliably for VCO frequencies below 30MHz.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, AV
DD
/ V
DD
= 5.0V ± 10%
Symbol
V
IH
V
IL
V
OH
V
OL
V
H
I
OZ
I
IN
I
PD
Parameter
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input Hysteresis
Output Leakage Current
Input Leakage Current
Input Pull-Down Current (PE)
Conditions
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
DD
= Min., I
OH
=
−24mA
V
DD
= Min., I
OH
=
−100µA
V
DD
= Min., I
OL
= 24mA
V
DD
= Min., I
OL
= 100µA
—
V
OUT
= V
DD
or GND, V
DD
= Max.
V
IN
= AV
DD
or GND, AV
DD
= Max.
AV
DD
= Max., V
IN
= AV
DD
Min.
2
—
2.4
3
—
—
—
—
—
—
Typ.
—
—
—
—
—
—
100
—
—
—
Max.
—
0.8
—
—
0.45
0.2
—
5
5
100
Unit
V
V
V
V
V
V
mV
µA
µA
µA
POWER SUPPLY CHARACTERISTICS
Symbol
I
DDQ
∆I
DD
I
DDD
Parameter
Quiescent Power Supply Current
Power Supply Current per Input HIGH
Dynamic Power Supply Current
(1)
Test Conditions
V
DD
= Max., OE/RST = LOW,
SYNC = LOW, All outputs unloaded
V
DD
= Max., V
IN
= 3.4V
V
DD
= Max., C
L
= 0pF
Typ.
Max.
1.5
1.5
0.4
Unit
mA
mA
mA/MHz
0.5
0.2
NOTE:
1. Relative to the frequency of Q outputs.
4
QS5919T
LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
INPUT TIMING REQUIREMENTS
Symbol
t
R
, t
F
F
I
t
PWC
D
H
Description
(1)
Maximum input rise and fall times, 0.8V to 2V
Input Clock Frequency, SYNC
0
, SYNC
1 (1)
Input clock pulse, HIGH or LOW
(2)
Input duty cycle
(2)
Min.
—
2.5
2
25
Max.
3
F
MAX _2XQ
—
75
Unit
ns
MHz
ns
%
NOTES:
1. See Output Frequency and Frequency Selection tables for more detail on allowable SYNC input frequencies for different speed grades with
different FEEDBACK and FREQ_SEL combinations.
2. Where pulse witdh implied by D
H
is less than t
WPC
limit, t
WPC
limit applies
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
t
SKR
t
SKF
t
SKALL
t
PW
t
PW
t
J
t
PD
t
LOCK
t
PZH
t
PZL
t
PHZ
t
PLZ
t
R,
t
F
Parameter
(1)
Output Skew Between Rising Edges, Q
0
-Q
4
and Q/
2
(2)
Output Skew Between Falling Edges, Q
0
-Q
4
and Q/
2
(2)
Output Skew, All Outputs
(2,5)
Pulse Width, 2xQ output, >40MHz
Pulse Width, Q
0
-Q
4
, Q
5,
Q/
2
outputs, 80MHz
Cycle-to-Cycle Jitter
(4)
SYNC Input to Feedback Delay
(6)
SYNC to Phase Lock
Output Enable Time, OE/RST LOW to HIGH
(3)
Output Enable Time, OE/RST HIGH to LOW
(3)
Output Rise/Fall Times, 0.8V
∼
2V
Min.
—
—
—
T
CY
/2
−
0.4
T
CY
/2
−
0.4
−
0.15
−
500
—
0
0
0.3
Max.
350
350
500
T
CY
/2 + 0.4
T
CY
/2 + 0.4
0.15
0
10
7
6
1.5
Unit
ps
ps
ps
ns
ns
ns
ps
ms
ns
ns
ns
NOTES:
1. See Test Loads and Waveforms for test load and termination. Test circuit 1 is used for output enable/disable parameters. Test circuit 2 is used for all
other timing parameters.
2. Skew specifications apply under identical environments (loading, temperature, V
CC
, device speed grade).
3. Measured in open loop mode PLL_EN = 0.
4. Jitter is characterized with Q output at 20MHz. See FREQUENCY SELECTION TABLE for information on proper FREQ_SEL level for specified input
frequencies.
5. Skew measured at selected synchronization edge.
6. t
PD
measured at device inputs at 1.5V, Q output at 80MHz.
