QS5LV931
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
3.3V LOW SKEW CMOS PLL
CLOCK DRIVER WITH
INTEGRATED LOOP FILTER
FEATURES:
DESCRIPTION:
QS5LV931
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3.3V operation
JEDEC LVTTL compatible level
Clock input is 5V tolerant
Q outputs, Q/2 output
<300ps output skew, Q
0
–Q
4
Outputs 3-state and reset while OE/RST low
PLL disable feature for low frequency testing
Internal loop filter RC network
Internal VCO/2 option
Balanced drive outputs ±24mA
ESD >2000V
80MHz maximum frequency
Available in QSOP package
The QS5LV931 Clock Driver uses an internal phase locked loop
(PLL) to lock low skew outputs to a reference clock input. Six outputs
are available: Q
0
–Q
4
, Q/2. Careful layout and design ensure <300ps
skew between the Q
0
–Q
4
, and Q/2 outputs. The QS5LV931 includes
an internal RC filter which provides excellent jitter characteristics and
eliminates the need for external components. Various combinations of
feedback and a divide-by-2 in the VCO path allow applications to be
customized for linear VCO operation over a wide range of input SYNC
frequencies. The PLL can also be disabled by the PLL_EN signal to
allow low frequency or DC testing. The QS5LV931 is designed for use
in cost sensitive high-performance computing systems, workstations,
multi-board computers, networking hardware, and mainframe systems.
Several can be used in parallel or scattered throughout a system for
guaranteed low skew, system-wide clock distribution networks. In the
QSOP package, the QS5LV931 clock driver represents the best value
in small form factor, high-performance clock management products.
For more information on PLL clock driver products, see Application
Note AN-227.
FUNCTIONAL BLOCK DIAGRAM
FEEDBACK
PLL_EN
FREQ_SEL
SYNC
O E/RST
PH ASE
DETE CTO R
LOO P
FILTER
0
1
VCO
1
/2
0
R
D
R
D
R
D
R
D
R
D
R
D
Q
Q
Q
Q
Q
Q
Q
Q/
2
Q
4
Q
3
Q
2
Q
1
Q
0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
c
2002
Integrated Device Technology, Inc.
JANUARY 2002
DSC-5821/2
QS5LV931
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
DC Input Voltage V
IN
Maximum Power Dissipation (T
A
= 85°C)
T
STG
Storage Temperature Range
Max
–0.5 to +7
–0.5 to +5.5
0.5
–65 to +150
Unit
V
V
W
°C
AV
DD
/V
DD
Supply Voltage to Ground
GND
OE/RST
FEEDBACK
AV
DD
V
DD
AGND
SYNC
FREQ_SEL
GND
Q
1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q
4
Q/2
GND
Q
3
V
DD
Q
2
GND
PLL_EN
GND
Q
1
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
CAPACITANCE
(T
A
= +25°C, f = 1MHz, V
IN
= 0V)
Pins
C
IN
C
OUT
Typ.
3
4
Max.
4
5
Unit
pF
pF
QSOP
TOP VIEW
PIN DESCRIPTION
Pin Name
SYNC
FREQ_SEL
FEEDBACK
Q
0
-Q
4
Q/2
OE/RST
PLL_EN
V
DD
AV
DD
GND
AGND
I/O
I
I
I
O
O
I
I
—
—
—
—
Description
Reference clock input
VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency. HIGH is for higher frequencies,
LOW is for lower frequencies.
PLL feedback input which is connected to either a Q or a Q/2 output. External feedback provides flexibility for different output frequency
relationships. See the Frequency Selection Table for more information.
Clock outputs
Clock output. Matched in phase, but frequency is half the Q frequency.
Output enable/asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1, outputs are
enabled.
PLL enable. Enables and disables the PLL. Allows the SYNC input to be single-stepped for system debug.
Power supply for output buffers
Power supply for phase lock loop and other internal circuitries
Ground supply for output buffers
Ground supply for phase lock loop and other internal circuitries
OUTPUT FREQUENCY SPECIFICATIONS
Industrial: T
A
= –40°C to +85°C, AV
DD
/V
DD
= 3.3V ± 0.3V
Symbol
F
MAX_Q
F
MAX_Q/2
F
MIN_Q
F
MIN_Q/2
Description
Max Frequency, Q
0
- Q
4
,
Max Frequency, Q/2
Min Frequency, Q
0
- Q
4
Min Frequency, Q/2
– 50
50
25
10
5
– 66
66
33
10
5
– 80
80
40
10
5
Units
MHz
MHz
MHz
MHz
2
QS5LV931
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
FREQUENCY SELECTION TABLE
SYNC (MHz)
Output Used for
FREQ_SEL
HIGH
HIGH
LOW
LOW
Feedback
Q/2
Q
0
-Q
4
Q/2
Q
0
-Q
4
Min.
F
MIN_Q/2
F
MIN_Q
F
MIN_Q/2
/2
F
MIN_Q
/2
(allowable range)
(1)
Max
F
MAX _Q/2
F
MAX _Q
F
MAX _Q/2
/2
F
MAX _Q
/2
Output Frequency Relationships
Q/2
SYNC
SYNC / 2
SYNC
SYNC / 2
Q
0
- Q
4
SYNC X 2
SYNC
SYNC X 2
SYNC
NOTE:
1. Operation in the specified SYNC frequency range guarantees that the VCO will operate in its optimal range of 20MHz to F
MAX_Q
x2. Operation with Sync inputs outside specified
frequency ranges may result in out-of-lock outputs. FREQ_SEL only affects VCO frequency and does not affect output frequencies.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, AV
DD
/V
DD
= 3.3V ± 0.3V
Symbol
V
IH
V
IL
V
OH
V
OL
V
H
I
OZ
I
IN
Parameter
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input Hysteresis
Output Leakage Current
Input Leakage Current
Conditions
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
I
OH
=
−
24mA
I
OH
=
−
100µA
V
DD
= Min., I
OL
= 100µA
—
V
OUT
= V
DD
or GND,
V
DD
= Max., Outputs Disabled
AV
DD
= Max., V
IN
= AV
DD
or GND
—
—
5
µA
Min.
2
—
V
DD
— 0.6
V
DD
— 0.2
—
—
—
—
Typ.
—
—
—
—
—
—
100
—
Max.
—
0.8
—
—
0.45
0.2
—
5
mV
µA
V
Unit
V
V
V
V
DD
= Min., I
OL
= 24mA
POWER SUPPLY CHARACTERISTICS
Symbol
I
DDQ
∆I
DD
I
DDD
Parameter
Quiescent Power Supply Current
Power Supply Current per Input HIGH
Dynamic Power Supply Current per Output
Test Conditions
V
DD
= Max., OE/RST = LOW,
SYNC = LOW, All outputs unloaded
V
DD
= Max., V
IN
= 3V
V
DD
= Max., C
L
= 0pF
1
0.2
30
0.3
µA
µA/MHz
Typ.
—
Max.
1
Unit
mA
INPUT TIMING REQUIREMENTS
Symbol
t
R
, t
F
F
I
t
PWC
D
H
Input Clock Frequency, SYNC
Duty Cycle, SYNC
(2)
(1)
Description
(1)
Maximum input rise and fall times, 0.8V to 2V
Input clock pulse, HIGH or LOW
(2)
Min.
—
2.5
2
25
Max.
3
F
MAX _Q
—
75
Unit
ns
MHz
ns
%
NOTES:
1. See Output Frequency and Frequency Selection tables for more detail on allowable SYNC input frequencies for different speed grades with different FEEDBACK and FREQ_SEL
combinations.
2. Where pulse witdh implied by D
H
is less than t
WPC
limit, t
WPC
limit applies
3
QS5LV931
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
t
SKR
t
SKF
t
PW
t
J
t
PD
t
LOCK
t
PZH
t
PZL
t
PHZ
t
PLZ
t
R,
t
F
Output Rise/Fall Times, 0.8V
~
2V
0.3
2
ns
Output Disable Time, OE/RST HIGH to LOW
(3)
0
14
ns
Parameter
(1)
Output Skew Between Rising Edges, Q
0
-Q
4
and Q/2
(2)
Output Skew Between Falling Edges, Q
0
-Q
4
and Q/2
(2)
Pulse Width, Q
0
-Q
4
, Q/2 outputs, 80MHz
Cycle-to-Cycle Jitter
(4)
SYNC Input to Feedback Delay
(5)
SYNC to Phase Lock
Output Enable Time, OE/RST LOW to HIGH
(3)
Min.
—
—
T
CY
/2
−
0.4
— 0.15
Max.
300
300
T
CY
/2 + 0.4
0.15
500
10
14
Unit
ps
ps
ns
ns
ps
ms
ns
−
500
—
0
NOTES:
1. See Test Loads and Waveforms for test load and termination.
2. Skew specifications apply under identical environments (loading, temperature, V
DD
, device speed grade).
3. Measured in open loop mode PLL_EN = 0.
4. Jitter is characterized with Q output at 20MHz. See Frequency Selection Table for information on proper FREQ_SEL level for specified input frequencies.
5. t
PD
measured at device inputs at 0.5V
DD
, Q output at 80MHz.
4
QS5LV931
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
AC TEST LOADS AND WAVEFORMS
V
DD
300
Ω
6.0V
OUTPUT
100
Ω
OUTPUT
300
Ω
30pF
100
Ω
Test Circuit 1
Test Circuit 2
1.0ns
1.0ns
t
R
3.0V
2.0V
0.5V
D D
0.8V
0V
t
P W
t
F
3.0V
2.0V
V
th
= 0.5V
D D
0.8V
0V
CMOS Input Test Waveform
EN ABLE
DISABLE
CMOS Output Waveform
3V
0.5V
D D
CONTROL
INPU T
t
PZ L
OUTPUT
NOR MALLY
LOW
SWITCH
CLO SED
0.5V
DD
0.3V
t
PZH
SWITCH
OUTPUT
NOR MALLY
HIGH
OPEN
0.5V
DD
t
PHZ
0.3V
V
O H
V
OL
t
PLZ
3.0V
0V
0V
Enable and Disable Times
TEST CIRCUIT 1 is used for output enable/disable parameters.
TEST CIRCUIT 2 is used for all other timing parameters.
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