QS74LVCH16245A ADVANCE INFORMATION
Q
Q
UALITY
S
EMICONDUCTOR,
I
NC.
High-Speed CMOS 3.3V
16-Bit Bidirectional Transceiver
with Bus Hold
DESCRIPTION
QS74LVCH16245A
ADVANCE
INFORMATION
FEATURES/BENEFITS
• 5V tolerant inputs and outputs
• Bus Hold feature holds last active state during
3-state operation
• 10µA I
CCQ
quiescent power supply current
• Hot insertable
• 2.0V–3.6V V
CC
supply operation
•
±24mA
balanced output drive
• Power down high impedance inputs and outputs
• t
PD
=4.0 ns max.
• Input hysteresis for noise immunity
• Meets or exceeds JEDEC Standard 36
specifications
• Multiple power and ground pins for low noise
• Operating temperature range:
–40°C to 85°C
• Latch-up performance exceeds 500mA
• ESD performance:
Human body model > 2000V
Machine model > 200V
• Packages available:
48-pin TSSOP
48-pin SSOP
Figure 1. Functional Block Diagram
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The QS74LVCH16245A is a 16-bit transceiver that is
ideal for driving bidirectional address and data buses.
This device can be used as either two independent
8-bit transceivers or one 16-bit transceiver deter-
mined by the Direction and Output Enable controls.
The 3.3V LVC family features low power, low switch-
ing noise, and fast switching speeds for low power
portable applications as well as high-end, advanced
workstation applications. 5V tolerant inputs and out-
puts allow this LVC product to be used in mixed 5V
and 3.3V applications. Active Bus Hold feature on
LVCH16245A retains last valid logic state at unused
or floating data inputs, thus eliminating the need for
external pull-up resistors. Easy board layout is facili-
tated by the use of flow-through pinouts and byte
enable controls provide architectural flexibility for
systems designers. To accommodate hot-plug or
live insertion applications, this product is designed
not to load an active bus when V
CC
is removed.
However, during power up or power down sequence,
OE
should be tied to V
CC
to ensure high-impedance
state on the outputs.
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1DIR
2DIR
1OE
1Ax
1Bx
2Ax
2OE
2Bx
MDSL-00340-00
SEPTEMBER 10, 1998
QUALITY SEMICONDUCTOR, INC.
1
QS74LVCH16245A ADVANCE INFORMATION
Figure 2. Pin Configuration
(All Pins Top View)
SSOP, TSSOP
1DIR
1B1
1B2
GND
1B3
1B4
V
CC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
V
CC
2B5
2B6
GND
2B7
2B8
2DIR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1A1
1A2
GND
1A3
1A4
V
CC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
V
CC
2A5
2A6
GND
2A7
2A8
2OE
Table 1. Pin Description
Name
xDIR
xOE
xAx
xBx
Description
Transmit/Receive Input
Output Enable Inputs
Bus A
Bus B
Table 2. Function Table
Inputs
xOE
OE
L
L
H
xDIR
L
H
X
Outputs
Bus B Data to Bus A
Bus A Data to Bus B
Hi-Z
Table 3. Absolute Maximum Ratings
Supply Voltage to Ground ................................. –0.5V to 7.0V
DC Output Voltage V
OUT
Outputs HIGH-Z ............................................. –0.5V to 7.0V
Outputs Active ..................................... –0.5V to V
CC
+ 0.5V
DC Input Voltage V
IN
......................................... –0.5V to 7.0V
DC Input Diode Current with V
IN
< 0 ........................... –50mA
DC Output Diode Current
V
O
< 0 ...................................................................... –50mA
V
O
> V
CC
.................................................................... 50mA
DC Output Source/Sink Current (I
OH
/I
OL
) ....................
±50mA
DC Supply Current per Supply Pin ...........................
±100mA
DC Ground Current per Ground Pin .........................
±100mA
T
STG
Storage Temperature ............................ –65°C to 150°C
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V
CC
V
IH
V
IL
V
IN
V
OUT
I
OH
I
OL
∆t/∆v
T
A
Note:
Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to this device resulting in
functional or reliability type failures.
Table 4. Recommended Operating Conditions
Symbol Parameter
Supply Voltage, Operating
Supply Voltage, Data Retention Only
Input HIGH Voltage
Input LOW Voltage
Input Voltage
Output Voltage in Active State
Output Voltage in “OFF” State
Output Current HIGH V
CC
= 3.0–3.6V
V
CC
= 2.7V
Output Current LOW V
CC
= 3.0–3.6V
V
CC
= 2.7V
Input Transition Slew Rate
Operating Free Air Temperature
V
OL
= 2.7 to 3.6V
V
CC
= 2.7 to 3.6V
Min
2.0
1.5
2.0
—
0
0
0
—
—
—
—
–40
Max
3.6
3.6
—
0.8
5.5
V
CC
5.5
–24
–12
24
12
10
85
ns/V
°C
mA
mA
V
V
V
V
Unit
V
2
QUALITY SEMICONDUCTOR, INC.
MDSL-00340-00
SEPTEMBER 10, 1998
QS74LVCH16245A ADVANCE INFORMATION
Table 5. DC Electrical Characteristics Over Operating Range
Industrial Temperature Range, T
A
= –40°C to 85°C
Symbol
V
OH
Parameter
Output HIGH Voltage
Test Conditions
V
CC
= 2.7V, I
OH
= –100µA
V
CC
= 2.7V, I
OH
= –12mA
V
CC
= 3.0V, I
OH
= –12mA
V
CC
= 3.0V, I
OH
= –24mA
V
CC
= 2.7V, I
OL
= 100µA
V
CC
= 2.7V, I
OL
=12mA
V
CC
= 3.0V, I
OL
= 24mA
V
CC
= 2.7V, I
IN
= –18mA
V
I
= 0V, V
I
= 5.5V, V
CC
= 3.6V
V
CC
= 3.6V
V
IN
= 0V or V
IN
= V
CC
V
CC
= 3.6V, 0.8V
≤
V
IN
≤
2.0V
V
CC
= 3V
V
IN
= 2.0V
V
IN
= 0.8V
V
O
= 0V, V
O
= 5.5V,
V
I
= V
IH
or V
IL,
V
CC
= 3.6V
V
CC
= 0V, V
I
or V
O
= 5.5V
Min
V
CC
–0.2
2.2
2.4
2.2
—
—
—
—
—
—
—
–75
75
—
Typ
(1)
—
—
—
—
—
—
—
–0.7
—
—
—
—
—
Max
—
—
—
—
0.2
0.4
0.55
–1.2
±1.0
50
500
(4)
—
—
µA
Unit
V
V
OL
Output LOW Voltage
V
V
IK
I
I
I
BH
Input Clamp Voltage
Input Leakage Current
Input Current
Input HIGH or LOW
Bus Hold Inputs
(2,3)
Bus Hold Sustaining
Current
Bus Hold Inputs
High-Z I/O Leakage
Power Off Leakage
V
µA
µA
I
BHH
I
BHL
I
OZ
I
OFF
I
CC
∆I
CC
Quiescent Power Supply V
CC
= 3.6V, V
IN
= V
CC
or GND
Current
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—
—
—
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—
±1.0
10
—
0.1
2.0
10
3.0
75
500
µA
µA
µA
µA
4
Quiescent Power Supply V
CC
= 3.6V, V
IN
= V
CC
– 0.6V
(5)
Current per Control
Inputs at TTL HIGH
Quiescent Power Supply V
CC
= 3.6V, V
IN
= V
CC
– 0.6V
(5)
Current per Bus Hold
Inputs at TTL HIGH
Notes:
1. Typical values are at V
CC
= 3.3V and T
A
= 25°C.
2. These parameters are guaranteed by characterization, but not production tested.
3. Pins with Bus Hold are identified in the Pin Description.
4. An external driver must provide at least
I
BH
during transition to guarantee that the Bus Hold input will change state.
5. Per TTL driven input. All other inputs at V
CC
or GND.
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MDSL-00340-00
SEPTEMBER 10, 1998
QUALITY SEMICONDUCTOR, INC.
3
QS74LVCH16245A ADVANCE INFORMATION
Table 6. Dynamic Switching Characteristics
Symbol Parameter
V
OLP
V
OLV
C
PD
Quiet Output
Dynamic Peak V
OL
Quiet Output
Dynamic Valley V
OL
Power Dissipation
Test Conditions
C
L
= 50pF, V
CC
= 3.3V V
IH
= 3.3V, V
IL
= 0V
C
L
= 50pF, V
CC
= 3.3V V
IH
= 3.3V, V
IL
= 0V
C
L
= 50pF, f = 10MHz, Output Enable
V
CC
= 3.6
±0.3V
Note:
1. Typical values are at V
CC
= 3.3V 25°C ambient.
Typ
(1)
Unit
0.8
0.8
20
4
V
V
pF
Output Disable
Table 7. Capacitance
(1)
Symbol
C
IN
C
I/O
Pins
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 0V, V
OUT
= 0V, f = 1MHz
V
IN
= 0V, V
OUT
= 0V, f = 1MHz
Typ
7.0
8.0
Note:
1. Capacitance is characterized but not production tested.
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pF
pF
Table 8. Switching Characteristics Over Operating Range
Industrial Temperature Range, T
A
= –40°C to 85°C.
C
LOAD
= 50pF, R
LOAD
= 500
Ω
unless otherwise noted.
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V
CC
= 3.3
±
0.3V
Min
1.5
1.5
1.5
—
Max
4.0
5.5
6.6
0.5
V
CC
= 2.7V
(2)
Min
1.5
1.5
1.5
—
Max
4.7
6.7
7.1
—
Unit
ns
ns
ns
ns
Symbol
t
PD
t
EN
t
DIS
t
SK(O)
Description
(1)
Propagation Delay
A to B, B to A
Output Enable Time
xOE, xDIR to A or B
Output Disable Time
(2)
xOE, xDIR to A or B
Output Skew
(3)
Notes:
1. Minimums guaranteed but not tested. See Test Circuit and Waveforms.
2. Guaranteed by characterization.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaran-
teed by characterization but not production tested.
4
QUALITY SEMICONDUCTOR, INC.
MDSL-00340-00
SEPTEMBER 10, 1998
QS74LVCH16245A ADVANCE INFORMATION
TEST CIRCUIT AND WAVEFORMS
Figure 3. Test Circuit
SWITCH POSITION
500Ω
6.0V
V
IN
Pulse
Generator
R
T
DUT
V
OUT
Test
Open Drain
Disable LOW
Enable LOW
Disable HIGH
Enable HIGH
All Other Inputs
Switch
6V
GND
Open
V
CC
50pF
C
L
500Ω
DEFINITIONS:
C
L
= Load capacitance: includes jig and
probe capacitance.
R
T
= Termination resistance: should be
equal to Z
OUT
of the Pulse Generator.
Figure 4. Setup, Hold, and
Release Timing
Data
Input
t
REM
Timing
Input
t
REM
Asychronous Control
Preset, Clear, Etc.
t
H
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
Figure 6. Pulse Width
Low-High-Low
Pulse
High-Low-High
Pulse
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1.5V
4
1.5V
Sychronous Control
Preset, Clear,
Clock Enable, Etc.
o
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Control
Input
t
PZL
Output
Normally
Low
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t
SU
t
H
Figure 5. Enable and Disable Timing
3V
1.5V
0V
Figure 7. Propagation Delay
3V
Same Phase
Input Transition
t
PLH
t
PHL
1.5V
0V
V
OH
1.5V
Output
t
PLH
t
PHL
Opposite Phase
Input Transition
V
OL
3V
1.5V
0V
3.0V
Switch
Closed
t
PZL
1.5V
0.3V
3.0V
V
OL
V
OH
0V
Output
Normally
High
Switch
Open
0.3V
1.5V
0V
Notes:
1. Input Control Enable = LOW and Input Control
Disable = HIGH.
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz;
Z
OUT
≤
50Ω; t
F
, t
R
≤
2.5ns.
MDSL-00340-00
SEPTEMBER 10, 1998
QUALITY SEMICONDUCTOR, INC.
5
DSP 与 ARM 处理器
