DUAL IN-LINE PACKAGES
Q-TECH
CORPORATION
CRYSTAL CLOCK OSCILLATORS
-5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.01Hz to 200MHz
Description
Features
Q-Tech’s Dual In-line (DIP) crystal oscillators
consist of a source clock square wave generator, logic
output buffers and/or logic divider stages, and a
round AT high-precision quartz crystal built in a
metal through-hole package in DIP-8 or DIP-14
configurations.
• Made in the USA
• ECCN: EAR99
• DFARS 252-225-7014 Compliant:
Electronic Component Exemption
• USML Registration # M17677
• Wide frequency range from 0.01Hz to 200MHz
• Available as QPL MIL-PRF-55310/8, /11, /14, /15,
/16, /17, /18, /25, and /26
• Wide operating temperature range
• Choice of output logic options
• Supply voltages from 1.8Vdc to 15Vdc
• Lower or higher supply voltages available
• All metal hermetically sealed package
• Tight or custom symmetry available
• Fast rise and fall times
• Fast start-up time
• Capacitive load drive capability (Z output)
• Multiple outputs available
• Fundamental and third overtone designs
• High operating temperature up to +225ºC
• Custom design available tailors to meet customer’s
needs
• Q-Tech does not use pure lead or pure tin in its
products
• RoHS compliant
Ordering Information
Model #
C
AC
HC
T
L
N
R
E
EH
EF
PE
LP
Z
=
=
=
=
=
=
=
=
=
=
=
=
=
QTXX — XX— D — XX — M — 20.000MHz
Tristate Option D
(Left blank if no Tristate)
CMOS +5V to +15V *
ACMOS +5V
HCMOS +5V
TTL +5V
LVHCMOS +3.3V
LVHCMOS +2.5V
LVHCMOS +1.8V
10K ECL -5.2V
10KH ECL -5.2V
100K/300K ECL -4.5V
PECL +5V
PECL +3.3V
Z output
Screened to
MIL-PRF-55310,level B
(Left blank if no screening)
1
3**
4
5
6
9
10
11
12
=
=
=
=
=
=
=
=
=
±
±
±
±
±
±
±
±
±
100ppm
5ppm
50ppm
25ppm
50ppm
50ppm
100ppm
50ppm
100ppm
at
at
at
at
at
at
at
at
at
0ºC
0ºC
0ºC
-20ºC
-55ºC
-55ºC
-55ºC
-40ºC
-40ºC
Output frequency
For Non-Standard requirements, contact Q-Tech Corporation at Sales@Q-Tech.com
Frequency stability vs. temperature codes may not be available in all frequencies.
Q-Tech will assign a custom part number for custom specifications and all high
temperature applications with typical frequency stability at ± 250ppm up to +200ºC.
(*) Please specify supply voltage when ordering CMOS
(**) Require an external capacitor
to +70ºC
to +50ºC
to +70ºC
to +70ºC
to +105ºC
to +125ºC
to +125ºC
to +85ºC
to +85ºC
Applications
• Designed to meet today’s requirements for all
voltage applications
• Wide military clock applications
• Smart munitions
• Navigation
• Industrial controls
• Microcontroller driver
• Down-hole applications up to +225ºC
• Package material (header and leads): Kovar
• Lead finish:
Gold Plated – 50µ ~ 80µ inches
Nickel Underplate – 100µ ~ 250µ inches
• Cover (DIP-14): Pure Nickel Grade A (DIP-8): Stainless Steel
• Package to lid attachment: Resistance weld
• Standard packaging in black foam
• Optional anti-static plastic tube
•
•
•
•
Package Information
Packaging Options
Other Options Available For An Additional Charge
Lead forming available on all packages. Please contact for details.
Solder Dip Sn/Pb 60/40%
P. I. N. D. test
Lead trimming
All DIP packages are available in surface mount form.
Specifications subject to change without prior notice.
Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-t ec h.com
Dual In-line Packages (Revision B, July 2008) (ECO# 9354)
1
DUAL IN-LINE PACKAGES
Electrical Characteristics
Output freq. range (Fo)
Supply voltage (Vdd)
Freq. stability (∆F/∆T)
CORPORATION
Q-TECH
CRYSTAL CLOCK OSCILLATORS
-5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.01Hz to 200MHz
C
AC
HC
T
L (*)
ECL / PECL (**)
1MHz — 200MHz
1MHz — 110MHz
-5.2Vdc ± 5% (10K / 10KHECL)
5Vdc ± 5% (PECL)
3.3Vdc ± 5% (LVPECL)
Parameters
DIP 14
DIP 8
0.01Hz — 15MHz
245Hz — 15MHz
5V ~ 15Vdc ± 10%
0.01Hz — 160MHz
0.01Hz — 85MHz
0.01Hz — 160MHz
0.01Hz — 85MHz
5.0Vdc ± 10%
0.01Hz — 160MHz
10Hz — 85MHz
0.01Hz — 160MHz
0.01Hz — 100MHz
3.3Vdc ± 10%
Operating temp. (Topr)
Storage temp. (Tsto)
F and Vdd dependent
3 mA max. at 5V up to 5MHz
25 mA max. at 15V up to 15MHz
20 mA max. - 0.01Hz ~
25 mA max. - 16MHz ~
35 mA max. - 40MHz ~
45 mA max. - 60MHz ~
55 mA max. - 85MHz ~
65 mA max. - 110MHz ~
75 mA max. - 125MHz ~
See Option codes
< 16MHz
< 40MHz
< 60MHz
< 85MHz
< 110MHz
< 125MHz
160MHz
-62ºC to + 125ºC
See Option codes
Operating supply current
(Idd) (No Load)
Symmetry
(50% of ouput waveform or
1.4Vdc for TTL)
Rise and Fall times (Tr/Tf)
(with typical load)
Output Load
45/55% max. Fo < 4MHz
40/60% max. Fo ≥ 4MHz
30ns max.
(Measured from 10% to 90%)
15pF // 10kΩ
0.9 x Vdd min.; 0.1 x Vdd max.
15ns max. Fo < 15kHz
6ns max. Fo 15kHz ~ 39.999MHz
3ns max. Fo 40MHz ~ 160MHz
(Measured from 10% to 90% CMOS or from 0.8V to 2.0V TTL)
10TTL Fo < 20MHz
6TTL Fo ≥ 20MHz
45/55% max. Fo < 12MHz
40/60% max. Fo ≥ 12MHz
3 mA max. - 0.01Hz ~ < 500kHz
6 mA max. - 500kHz ~ < 16MHz
10 mA max. - 16MHz ~ < 32MHz
20 mA max. - 32MHz ~ < 60MHz
30 mA max. - 60MHz ~ < 100MHz
40 mA max. - 100MHz ~ < 130MHz
50 mA max. - 130MHz ~ 160MHz
45 mA max. - 1MHz ~ < 125MHz
75 mA max. - 125MHz ~ 200MHz
3.5ns max. Fo < 125MHz
3ns max. Fo 125MHz ~ 200MHz
15pF // 10kΩ
0.9 x Vdd min.; 0.1 x Vdd max.
± 4mA .
(Measured from 20% to 80%)
50Ω to -2V (10K / 10KH)
50Ω to Vcc -2V (P & LP)
45/55% max. Fo < 12MHz
40/60% max. Fo ≥ 12MHz
Start-up time (Tstup)
Output voltage (Voh/Vol)
Output Current (Ioh/Iol)
± 1mA typ. at 5V
± 6.8mA typ. at 15V
Call for details
10ms max.
2.4V min.; 0.4V max.
-1.6mA / TTL
+40µA / TTL
Enable/Disable
Tristate function Pin 1
Aging (at 70ºC)
± 24mA
Jitter RMS 1σ (at 25ºC)
VIH ≥ 2.2V Oscillation;
VIL ≤ 0.8V High Impedance
8ps typ. - < 40MHz
5ps typ. - ≥ 40MHz
±8 mA
-1.15V min; -1.54V max. (E)
4V min.; 3.37V max. (PE)
2.27V min.; 1.68V max. (LP)
-50mA
Call for details
DIP 14: QT6, QT18, QT41, QT42, QT47
DIP 8: QT50, QT51, QT55
Q-TECH Corporation
-
± 5ppm max. first year / ± 2ppm typ. per year thereafter
VIH ≥ 0.7 x Vdd Oscillation;
VIL ≤ 0.3 x Vdd High Impedance
15ps typ. - < 40MHz
8ps typ. - ≥ 40MHz
Integrated phase jitter
12kHz - 20MHz 1ps typ.
(*) Available in 2.5Vdc (N) or 1.8Vdc (R)
(**) Please contact Q-Tech for details on 100KECL logic (EF)
Z Output logic can drive up to 200 pF load with typical 6ns rise & fall times (tr, tf)
-
www.q-t ec h.c om
10150 W. Jefferson Boulevard, Culver City 90232
-
Tel: 310-836-7900 - Fax: 310-836-2157
Dual In-line Packages (Revision B, July 2008) (ECO# 9354)
2
DUAL IN-LINE PACKAGES
Q-TECH
Package Configuration Versus Pin Connections
A
B
C
CORPORATION
CRYSTAL CLOCK OSCILLATORS
-5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.01Hz to 200MHz
DIP 14
QT6
Q-TECH
P/N
FREQ.
D/C S/N
Q-TECH
P/N
FREQ.
QT18
QT41
Q-TECH
P/N
FREQ.
D/C S/N
QT42
Q-TECH
P/N
FREQ.
D/C S/N
D
QT47
Q-TECH
P/N
FREQ.
D/C S/N
E
D/C S/N
.200
MAX.
(5.08)
.200
MIN.
(5.08)
.018
(.457)
.600
(15.24)
.880
MAX.
(22.35)
.018
(.457)
.600
(15.24)
.800
(20.32)
MAX.
.200
MAX.
(5.08)
.200
MIN.
(5.08)
.018
(.457)
.600
(15.24)
.800
(20.32)
MAX.
.200
MAX.
(5.08)
.200
MIN.
(5.08)
.018
(.457)
.600
(15.24)
.800
MAX.
(20.32)
.200 MAX.
(5.08)
.200
MIN.
(5.08)
.200 MAX.
.290 MAX.
(5.08)
(7.36)
.011
(.279)
.020
(.508)
.020
(.508)
.080 ± .010
(2.032±.254)
1
1
7
4
.505
MAX.
(12.83)
1
8
4
5
.505 MAX.
.300 (12.83)
(7.62)
.505 MAX.
.300 (12.83)
(7.62)
1
7
.505
MAX.
.300 (12.83)
(7.62)
1
14
7
8
.300
(7.62)
.505
MAX.
(12.83)
.300
(7.62)
14
8
14
8
8
.100
(2.54)
.100
(2.54)
5
ø .080
(ø 2.03)
.024
(.609)
.600
(15.24)
.800
(20.32)
MAX.
MAX
QT50
Q-TECH
P/N
FREQ.
D/C S/N
F
QT51
Q-TECH
P/N
FREQ.
D/C S/N
G
DIP 8
QT55
Q-TECH
P/N
FREQ.
D/C S/N
H
Equivalent
Output
QT # Conf Vcc GND Case
E/D Ext. Cap MIL-PRF-55310
(*)
Configuration
QT4
A
4
7
7
5
1 10 & 11
/14 = QT4T
QT6
QT10
QT12
QT18
QT41
.300
(7.62) SQ.
.505 SQ. MAX.
(12.83)
A
A
A
B
C
E
F
14
14
14
14
14
14
14
8
8
8
7
8
7
7
7
7
7
4
4
4
7
2
7
7
7
7
7
4
4
4
8
1
4
8
8
8
8
5
5
5
1
10 & 11
.200 MAX.
(5.08)
.250
MIN.
(6.35)
.018
(.457)
.020
(.508)
.200 MAX.
.290 MAX.
(5.080)
(7.366)
.011
(.279)
.080 ± .010
(2.032±.254)
.020
(.508)
.018
(.457)
.200 MAX.
(5.08)
.250
MIN.
(6.35)
N/A 10 & 11
1
1
1
1
1
1
1
1
10 & 11
10 & 11
N/A
N/A
N/A
N/A
N/A
N/A
/16 = QT6T
/17 = QT6T**
/18 = QT6C
/26A = QT6HC
/08 = QT10T
/11 = QT10C
/15 = QT10C
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
4
.505 SQ. MAX.
(12.83)
1
4
.505 SQ. MAX.
(12.83)
1
4
.300
(7.62) SQ.
.300 SQ.
(7.62)
8
5
.024
(.609)
.300
(7.62)
QT42
QT47
QT50
QT51
QT55
(*)
D
/26B = QT41HC
8
5
ø .060
(ø 1.52)
8
5
G
H
Dimensions are in inches (mm)
(**)
Gated Output, gate control pin 9.
ECL / PECL complimentary output available on pin 9 (For QT6 and
QT18 only) with a Q-Tech custom part number
Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-t ec h.com
Dual In-line Packages (Revision B, July 2008) (ECO# 9354)
3
DUAL IN-LINE PACKAGES
Q-TECH
Output Waveform (Typical)
SYMMETRY =
TH
T
TYPICAL SET-UP FOR START-UP TIME
CORPORATION
Startup Time
x 100%
CRYSTAL CLOCK OSCILLATORS
-5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.01Hz to 200MHz
Tr
VOH
Tf
Vdd
0.9xVdd
Oscilloscope
54616B Agilent
Variable Ramp
DUT
0.5xVdd
Ts
Start-up box
0.1xVdd
VOL
TH
GND
Test Circuit
T
TYPICAL TEST CIRCUIT FOR QT6T3 (6TTL)
+5VDC
0.01uF
OUTPUT
430
Typical test circuit for ECL logic.
mA
+
POWER
SUPPLY
-
+
Vdc
-
GND
OUT
OUT
Vcc
14
8
QT6T3
D1
50Ω
10k
10
11
7
12pF(*)
D2
0.1µF
or
0.01µF
-2Vdc
-4.5V
or
-5.2V
D3
D4
GND
Cext
D1-D4: 1N4148 or equivalent
(*) CL includes scope probe capacitance
Typical test circuit for CMOS logic
Typical test circuit for TTL logic.
Vdd
RL
+ mA
+
Power
supply
-
+
Vdc
Vdd Out
0.1µF
or
E/D GND
0.01µF
Output
+
POWER
SUPPLY
-
Ground
+
mA
-
+
Vdc
-
0.1µF
or
0.01µF
Vdd OUT
OUT
E/D GND
CL
Rs
-
15pF
(*)
10k
Tristate Function
Frequency vs. Temperature Curve
40
Frequency Stability (PPM)
30
20
10
0
-10
-20
-30
-40
-55
-45
-35
-25
The Tristate function on pin 1 has a built-in pull-up resistor typical 50kΩ, so it
can be left floating or tied to Vdd without deteriorating the electrical performance.
(*) CL includes probe and jig capacitance
LOAD
6 TTL
10 TTL
CL(*)
12pF
20pF
RL
430Ω
270Ω
RS
10kΩ
6kΩ
(*) CL inclides the loading effect of the oscilloscope probe.
FREQUENCY VERSUS TEMPERATURE QT6L9M-64.5MHz
-15
-5
5
15
25
35
45
55
65
75
85
95
105
115
125
Temperature (°C)
1_5
2_5
3_5
Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-t ec h.com
Dual In-line Packages (Revision B, July 2008) (ECO# 9354)
4
DUAL IN-LINE PACKAGES
Q-TECH
Thermal Characteristics
CORPORATION
CRYSTAL CLOCK OSCILLATORS
-5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.01Hz to 200MHz
The heat transfer model in a hybrid package is described in
figure 1 (Based on single ASIC design) .
D/A epoxy
Die
D/A epoxy
45º
Heat
Hybrid Case
45º
Substrate
Heat spreading occurs when heat flows into a material layer of
increased cross-sectional area. It is adequate to assume that
spreading occurs at a 45° angle.
The total thermal resistance is calculated by summing the
thermal resistances of each material in the thermal path
between the device and hybrid case.
RT = R1 + R2 + R3 + R4 + R5
R1
R2
R3
R4
R5
Die
D/A epoxy
The total thermal resistance RT (see figure 2) between the heat
source (die) to the hybrid case is the Theta Junction to Case
(Theta JC) in°C/W.
(Figure 1)
Substrate
D/A epoxy
Hybrid Case
T
CA
• Theta junction to case (Theta JC) for this product is 24°C/W.
• Theta case to ambient (Theta CA) for this part is 105°C/W.
• Theta Junction to ambient (Theta JA) is 130°C/W.
Maximum power dissipation PD for this package at 25°C is:
• PD(max) = (TJ (max) – TA)/Theta JA
• With TJ = 175°C (Maximum junction temperature of die)
• PD(max) = (175 – 25)/130 = 1.15W
A
T
C
JC
T
J
Die
JC
CA
JA
(Figure 2)
Environmental Specifications
Q-Tech Standard Screening/QCI (MIL-PRF55310) is available for all of our DIP packages. Q-Tech can also customize screening and
test procedures to meet your specific requirements. The DIP packages are designed and processed to exceed the following test
conditions:
Environmental Test
Temperature cycling
Constant acceleration
Seal Fine Leak
Burn-in
Aging
Vibration sinusoidal
Shock, non operating
Thermal shock, non operating
Ambient pressure, non operating
Resistance to solder heat
Moisture resistance
Terminal strength
Resistance to solvents
Solderability
Test Conditions
MIL-STD-883, Method 1010, Cond. B
MIL-STD-883, Method 2001, Cond. A, Y1
MIL-STD-883, Method 1014, Cond. A
160 hours, 125°C with load
30 days, 70°C, ± 0.7ppm max
MIL-STD-202, Method 204, Cond. D
MIL-STD-202, Method 213, Cond. I
MIL-STD-202, Method 107, Cond. B
MIL-STD-202, 105, Cond. C, 5 minutes dwell time minimum
MIL-STD-202, Method 210, Cond. C
MIL-STD-202, Method 106
MIL-STD-202, Method 211, Cond. C
MIL-STD-202, Method 215
MIL-STD-202, Method 208
Please contact Q-Tech for higher shock requirements
Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-t ec h.com
Dual In-line Packages (Revision B, July 2008) (ECO# 9354)
5
FPGA/CPLD
