R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
36-Mbit QDR™II SRAM
2-word Burst
REJ03C0341-0003
Preliminary
Rev. 0.03
Apr. 11, 2008
Description
The R1Q2A3636B is a 1,048,576-word by 36-bit, the R1Q2A3618B is a 2,097,152-word by 18-bit, and the
R1Q2A3609B is a 4,194,304-word by 9-bit synchronous quad data rate static RAM fabricated with advanced CMOS
technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a
burst counter. All input registers controlled by an input clock pair (K and /K) and are latched on the positive edge of K
and /K. These products are suitable for applications which require synchronous operation, high speed, low voltage, high
density and wide bit configuration. These products are packaged in 165-pin plastic FBGA package.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1.8 V
±
0.1 V power supply for core (V
DD
)
1.4 V to V
DD
power supply for I/O (V
DDQ
)
DLL circuitry for wide output data valid window and future frequency scaling
Separate independent read and write data ports with concurrent transactions
100% bus utilization DDR read and write operation
Two-tick burst for low DDR transaction size
Two input clocks (K and /K) for precise DDR timing at clock rising edges only
Two output clocks (C and /C) for precise flight time and clock skew matching-clock and data delivered together to
receiving device
Internally self-timed write control
Clock-stop capability with
µs
restart
User programmable impedance output
Fast clock cycle time: 4.0 ns (250 MHz)/5.0 ns (200 MHz)/6.0 ns (167 MHz)
Simple control logic for easy depth expansion
JTAG boundary scan
Notes: QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress
Semiconductor, IDT, NEC, Samsung, and Renesas Technology Corp.
Preliminary:
The specifications of this device are subject to change without notice. Please contact your nearest
Renesas Technology's Sales Dept. regarding specifications.
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 1 of
24
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
Ordering Information
Part Number
Organization
Cycle
time
4.0 ns
5.0 ns
6.0 ns
4.0 ns
5.0 ns
6.0 ns
4.0 ns
5.0 ns
6.0 ns
Clock
frequency
250 MHz
200 MHz
167 MHz
250 MHz
200 MHz
167 MHz
250 MHz
200 MHz
167 MHz
Package
Plastic FBGA 165-pin
PLBG0165FB-A
Notes
R1Q2A3636BBG-40R
1-M word
×
36-bit
R1Q2A3636BBG-50R
R1Q2A3636BBG-60R
R1Q2A3618BBG-40R
2-M word
×
18-bit
R1Q2A3618BBG-50R
R1Q2A3618BBG-60R
R1Q2A3609BBG-40R
4-M word
×
9-bit
R1Q2A3609BBG-50R
R1Q2A3609BBG-60R
Notes:
1. Part Number
(0:1)
R1 : Renesas Memory prefix
(2:3)
Q2 : QDRII 2-word Burst SRAM
Q3 : QDRII 4-word Burst SRAM
Q4 : DDRII 2-word Burst SRAM
Q5 : DDRII 4-word Burst SRAM
Q6 : DDRII 2-word Burst SRAM
Separate I/O
(4)
A : V
DD
=1.8V
(5:6)
36 : Density = 36Mb
72 : Density = 72Mb
(7:8)
36 : Organization = x36
18 : Organization = x18
09 : Organization = x9
(9)
(10:11)
(12:13)
(14)
(15)
(16)
R
: 1
st
Generation
A
: 2
nd
Generation
B
: 3
rd
Generation
BG
: Package type=BGA
60
: Cycle time=6.0 ns
50
: Cycle time=5.0 ns
40
: Cycle time=4.0 ns
33
: Cycle time=3.3 ns
R
: Temperature range= 0°C
∼70°C
I
: Temperature range= -40°C
∼85°C
B
: Pb-free
T
: Tape&Reel
S
: Pb-free and Tape&Reel
None
: Standard (Pb and Tray)
0
∼9
, A
∼Z
:Renesas internal use
2. Marking Name
Marking Name(0:14) =Part Number(0:14)
------------Pb
Marking Name(0:16) =Part Number(0:14)+Bx------------Pb-free
(Example) R1Q2A3609BBG-60R
------------Pb
R1Q2A3609BBG-60RB0 ------------Pb-free
(x=0
∼9
, A
∼Z)
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 2 of 24
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
Pin Arrangement
R1Q2A3636B
series
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
NC
4
5
6
7
8
9
10
NC
Q17
Q7
D15
D6
Q14
D13
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
/CQ
Q27
D27
D28
Q29
Q30
D30
/DOFF
D31
Q32
Q33
D33
D34
Q35
TDO
V
SS
Q18
Q28
D20
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
D18
D19
Q19
Q20
D21
Q22
V
DDQ
D23
Q23
D24
D25
Q25
Q26
SA
/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
/BW2
/BW3
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
/K
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
/C
/BW1
/BW0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
/R
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
SA
D17
D16
Q16
Q15
D14
Q13
V
DDQ
D12
Q12
D11
D10
Q10
Q9
SA
V
REF
Q4
D3
Q11
Q1
D9
D0
TMS
(Top View)
R1Q2A3618B
series
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
4
5
6
/CQ
NC
NC
NC
NC
NC
NC
/DOFF
NC
NC
NC
NC
NC
NC
TDO
V
SS
Q9
NC
D11
NC
Q12
D13
SA
D9
D10
Q10
Q11
D12
Q13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
V
DDQ
D14
Q14
D15
D16
Q16
Q17
SA
/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
/BW1
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
/K
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
/C
7
NC
8
9
/BW0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
/R
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
SA
NC
NC
NC
NC
NC
NC
10
NC
NC
Q7
NC
D6
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
(Top View)
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 3 of 24
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
R1Q2A3609B
series
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
4
5
6
/CQ
NC
NC
NC
NC
NC
NC
/DOFF
NC
NC
NC
NC
NC
NC
TDO
V
SS
NC
NC
D5
NC
NC
D6
SA
NC
NC
NC
Q5
NC
Q6
V
REF
NC
NC
Q7
NC
D8
NC
TCK
V
DDQ
NC
NC
D7
NC
NC
Q8
SA
/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
NC
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
/K
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
/C
7
NC
8
9
/BW
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
/R
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
SA
NC
NC
NC
NC
NC
NC
10
SA
NC
NC
NC
D3
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
V
REF
Q2
NC
NC
NC
NC
D0
TMS
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
(Top View)
Notes: 1. Address expansion order for future higher density SRAMs (i.e. 72Mb
→
144Mb
→288Mb):
(9A
→
3A
→
10A)
→
2A
→
7A
→
5B.
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 4 of 24
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
Pin Description
Name
SA
I/O type
Input
Descriptions
Synchronous address inputs: These inputs are registered and must meet the setup
and hold times around the rising edge of K for READ cycles and must meet the setup
and hold times around the rising edge of /K for WRITE cycles. All transactions operate
on a burst-of-two words (one clock period of bus activity). These inputs are ignored
when device is deselected.
Synchronous read: When low, this input causes the address inputs to be registered
and a READ cycle to be initiated. This input must meet setup and hold times around
the rising edge of K.
Synchronous write: When low, this input causes the address inputs to be registered
and a WRITE cycle to be initiated. This input must meet setup and hold times around
the rising edge of K.
Synchronous byte writes: When low, these inputs cause their respective byte to be
registered and written during WRITE cycles. These signals must meet setup and hold
times around the rising edges of K and /K for each of the two rising edges comprising
the WRITE cycle. See Byte Write Truth Table for signal to data relationship.
Input clock: This input clock pair registers address and control inputs on the rising
edge of K, and registers data on the rising edge of K and the rising edge of /K. /K is
ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and
hold times around the clock rising edges. These balls cannot remain V
REF
level.
Output clock: This clock pair provides a user-controlled means of tuning device output
data. The rising edge of /C is used as the output timing reference for first output data.
The rising edge of C is used as the output timing reference for second output data.
Ideally, /C is 180 degrees out of phase with C. C and /C may be tied high to force the
use of K and /K as the output reference clocks instead of having to provide C and /C
clocks. If tied high, C and /C must remain high and not to be toggled during device
operation. These balls cannot remain V
REF
level.
DLL disable: When low, this input causes the DLL to be bypassed for /DOFF Input
stable, low frequency operation.
Output impedance matching input: This input is used to tune the device outputs to the
system data bus impedance. Q and CQ output impedance are set to 0.2
×
RQ, where
RQ is a resistor from this ball to ground. This ball can be connected directly to V
DDQ
,
which enables the minimum impedance mode. This ball cannot be connected directly
to V
SS
or left unconnected.
IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left not TMS Input
connected if the JTAG function is not used in the circuit.
IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to V
SS
if the JTAG
function is not used TCK Input in the circuit.
Synchronous data inputs: Input data must meet setup and hold times around the rising
edges of K and /K during WRITE operations. See Pin Arrangement figures for ball site
location of individual signals.
The
×9
device uses D0 to D8. Remaining signals are not used.
The
×18
device uses D0 to D17. Remaining signals are not used.
The
×36
device uses D0 to D35.
Synchronous echo clock outputs: The edges of these outputs are tightly matched to
the synchronous data outputs and can be used as a data valid indication. These
signals run freely and do not stop when Q tristates.
IEEE 1149.1 test output: 1.8 V I/O level.
Synchronous data outputs: Output data is synchronized to the respective C and /C, or
to the respective K and /K if C and /C are tied high. This bus operates in response to
/R commands. See Pin Arrangement figures for ball site location of individual signals.
The
×9
device uses Q0 to Q8. Remaining signals are not used.
The
×18
device uses Q0 to Q17. Remaining signals are not used.
The
×36
device uses Q0 to Q35.
Notes
/R
Input
/W
Input
/BW
x
Input
K, /K
Input
C, /C
Input
/DOFF
ZQ
Input
Input
TMS
TDI
TCK
D
0
to D
n
Input
Input
Input
CQ, /CQ
Output
TDO
Q
0
to Q
n
Output
Output
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 5 of 24
