hinT=00000.0000
.
0000
.
1100
.
1100
--
-
00000.0000.0000.0000.0000---
00000.0000.0000.0000.000
0---
QDRII+_RL20
R1QGA72 / R1QKA72 Series
R1QGA7236ABG / R1QGA7218ABG
R1QKA7236ABG / R1QKA7218ABG
72-Mbit QDR™II+ SRAM
4-word Burst
Description
The R1Q#A7236 is a 2,097,152-word by 36-bit and the R1Q#A7218 is a 4,194,304-word by 18-bit synchronous
quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory
cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are controlled
by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are suitable
for applications which require synchronous operation, high speed, low voltage, high density and wide bit
configuration. These products are packaged in 165-pin plastic FBGA package.
# = A: Read Latency =2.5, w/o ODT
# = D: Read Latency =2.5, w/ ODT
#
= G: Read Latency =2.0, w/o ODT
#
= K: Read Latency =2.0, w/ ODT
R10DS0183EJ0011
Rev. 0.11
2013.01.15
Features
Power Supply
• 1.8 V for core (V
DD
), 1.4 V to V
DD
for I/O (V
DDQ
)
Clock
• Fast clock cycle time for high bandwidth
• Two input clocks (K and /K) for precise DDR timing at clock rising edges only
• Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems
• Clock-stop capability with
μs
restart
I/O
• Separate independent read and write data ports with concurrent transactions
• 100% bus utilization DDR read and write operation
• HSTL I/O
• User programmable output impedance
• DLL/PLL circuitry for wide output data valid window and future frequency scaling
• Data valid pin (QVLD) to indicate valid data on the output
Function
• Four-tick burst for reduced address frequency
• Internally self-timed write control
• Simple control logic for easy depth expansion
• JTAG 1149.1 compatible test access port
Package
• 165 FBGA package (15 x 17 x 1.4 mm)
Notes:
1.
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress
Semiconductor, IDT, Samsung, and Renesas Electronics Corp. (QDR Co-Development Team)
2. The specifications of this device are subject to change without notice. Please contact your nearest
Renesas Electronics Sales Office regarding specifications.
3. Refer to
"http://www.renesas.com/products/memory/fast_sram/qdr_sram/index.jsp"
for the latest and detailed information.
4. Descriptions about x9 parts in this datasheet are just for reference.
Rev. 0.11 : 2013.01.15
R10DS0183EJ0011
Common
R1QGA72 / R1QKA72 Series
Part Number Definition
Part Number Definition Table
Column No.
Example
0
1
2
3
4
5
6
2
7
1
8
9 10 11 - 12 13 14 15 16
-
2
5 R B 0
R 1 Q G A 7
8 A B G
The above part number is just example for 72M QDRII+ B4 x18 400MHz, 15x17mm PKG, Pb-free part.
No.
0-1
2-3
-
R1
Q2
Q3
Q4
Q5
Q6
QA
QB
QC
QD
QE
QF
QG
QH
QJ
QK
QL
QM
QN
QP
-
Comments
Renesas Memory Prefix
[*1]
[*2]
(L15)
QDR II B2
QDR II B4
(L15)
DDR II B2
(L15)
DDR II B4
(L15)
DDR II B2 SIO
(L15)
[*2]
QDR II+ B4 L25
DDR II+ B2 L25
DDR II+ B4 L25
QDR II+ B4 L25 w/ODT
DDR II+ B2 L25 w/ODT
DDR II+ B4 L25 w/ODT
QDR II+ B4 L20
DDR II+ B2 L20
DDR II+ B4 L20
QDR II+ B4 L20 w/ODT
DDR II+ B2 L20 w/ODT
DDR II+ B4 L20 w/ODT
QDR II+ B2 L20
QDR II+ B2 L20 w/ODT
-
[*4]
[*3]
No.
4
5-6
7-8
9
10-11
-
A
36
72
44
88
09
18
36
R
A
B
C
D
E
F
BG
BB
Comments
Vdd = 1.8 V
Density = 36Mb
Density = 72Mb
Density = 144Mb
Density = 288Mb
Data width = 9bit
Data width = 18bit
Data width = 36bit
1st Generation
2nd Generation
3rd Generation
4th Generation
5th Generation
6th Generation
7th Generation
PKG= BGA 15x17 mm
PKG= BGA 13x15 mm
No.
12-13
-
60
50
40
36
33
30
27
25
22
20
19
18
R
14
I
15
-
-
-
16
A
B
T
S
0 to 9,
A to Z Renesas internal use
or None
Comments
Frequency = 167MHz
Frequency = 200MHz
Frequency = 250MHz
Frequency = 275MHz
Frequency = 300MHz
Frequency = 333MHz
Frequency = 375MHz
Frequency = 400MHz
Frequency = 450MHz
Frequency = 500MHz
Frequency = 533MHz
Frequency = 550MHz
Commercial temp.
Ta range = 0 to 70
Industrial temp.
Ta range = -40 to 85
Pb-and Tray
Pb-free and Tray
Pb-and Tape&Reel
Pb-free and Tape&Reel
Note1:
[*1]
[*2]
[*3]
[*4]
B=Burst length (B2: Burst length=2, B4: Burst length=4)
L=Read Latency (L15: Read Latency = 1.5 cycle, L20: 2.0 cycle, L25: 2.5 cycle)
SIO=Separate I/O
ODT=On die termination
Note2:
Package Marking Name
Pb-parts: Marking Name = Part Number(0-14)
Pb-free parts: Marking Name = Part Number(0-14) + "PB-F"
(Example) R1QAA4436RBG-20R
Pb-F
----- Pb-parts
(Example)
R1QAA4436RBG-20R PB-F ----- Pb-free parts
Pb-free: RoHS Compliance Level = 5/6
Pb-free: RoHS Compliance Level = 6/6
R1Q*A series support both "Commercial" and "Industrial" temperatures
by "Industrial" temperature parts.
Note3:
Note4:
Rev. 0.11 : 2013.01.15
R10DS0183EJ0011
PAGE:2
hinS=11111.1111
.1111.1111.1111--
-
00000.0000.0000.0000.0000---
00000.0000.0000.0000.0000---072M
R1QGA72 / R1QKA72 Series
72M QDR/DDR SRAM (R1Q*A72 Series) Lineup
- Renesas supports or plans to support the parts listed below.
QDR II+ / DDR II+
Frequency (max)
(MHz)
Cycle Time (min)
(ns)
yy
Part Number
R1Q 2 A72 09 A Bv-
yy
R1Q 2 A72 18 A Bv-
yy
R1Q 2 A72 36 A Bv-
yy
R1Q 3 A72 18 A Bv-
yy
R1Q 3 A72 36 A Bv-
yy
R1Q 4 A72 18 A Bv-
yy
R1Q 4 A72 36 A Bv-
yy
R1Q 5 A72 18 A Bv-
yy
R1Q 5 A72 36 A Bv-
yy
R1Q 6 A72 18 A Bv-
yy
R1Q 6 A72 36 A Bv-
yy
R1Q A A72 18 A Bv-
yy
R1Q A A72 36 A Bv-
yy
R1Q B A72 18 A Bv-
yy
R1Q B A72 36 A Bv-
yy
R1Q C A72 18 A Bv-
yy
R1Q C A72 36 A Bv-
yy
R1Q D A72 18 A Bv-
yy
R1Q D A72 36 A Bv-
yy
R1Q E A72 18 A Bv-
yy
R1Q E A72 36 A Bv-
yy
R1Q F A72 18 A Bv-
yy
R1Q F A72 36 A Bv-
yy
R1Q G A72 18 A Bv-
yy
R1Q G A72 36 A Bv-
yy
R1Q H A72 18 A Bv-
yy
R1Q H A72 36 A Bv-
yy
R1Q J A72 18 A Bv-
yy
R1Q J A72 36 A Bv-
yy
R1Q K A72 18 A Bv-
yy
R1Q K A72 36 A Bv-
yy
R1Q L A72 18 A Bv-
yy
R1Q L A72 36 A Bv-
yy
R1Q M A72 18 A Bv-
yy
R1Q M A72 36 A Bv-
yy
Product
Type
Burst
Length
Latency
(Cycle)
ODT
Organi-
zation
533
500
450
2.22
-22
400
2.50
-25
375
2.66
-27
333
3.00
-30
333
3.00
-30
QDR II / DDR II
300
3.30
-33
250
4.00
-40
-40
-40
-30
-30
-30
-30
-33
-33
-33
-33
-40
-40
-40
-40
200
5.00
-50
-50
-50
No
1.875 2.00
-19
-20
1
2
3
5
6
8
9
11
12
14
15
17
18
20
21
23
24
26
27
29
30
32
33
35
36
38
39
41
42
44
45
47
48
50
51
B2
QDRII
B4
1.5
B2
DDRII
B4
DDRII
SIO
B2
No
QDRII+ B4
2.5
No
B2
DDRII+
B4
QDRII+ B4
Yes
2.5
B2
DDRII+
B4
QDRII+ B4
2.0
No
B2
DDRII+
B4
QDRII+ B4
B2
DDRII+
B4
Yes
2.0
x9
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
-19
-19
-19
-19
-19
-19
-20
-20
-20
-20
-20
-20
-22
-22
-22
-22
-22
-22
-25
-25
-25
-25
-25
-25
Notes:
1. "v" represents the
package size.
If "v" = "G" then size is 15 x 17 mm, and if "v" = "B" then 13 x 15 mm.
2. "yy" represents the
speed bin.
"R1QAA7236ABG-20" can operate at
500 MHz(max)
of frequency, for example.
3. The part which is not listed above is not supported, as of the day when this datasheet was issued,
in spite of the existence of the part number or datasheet.
Rev. 0.11 : 2013.01.15
R10DS0183EJ0011
PAGE:3
72---
R1QGA72 / R1QKA72 Series
Pin Arrangement
R1Q3A7236
(Top) /
R1QA(G)A7236
(Mid) /
R1QD(K)A7236
(Bottom)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
/CQ
Q27
D27
D28
Q29
Q30
D30
/DOFF
D31
Q32
Q33
D33
D34
Q35
TDO
2
NC
Q18
Q28
D20
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
3
SA
D18
D19
Q19
Q20
D21
Q22
V
DDQ
D23
Q23
D24
D25
Q25
Q26
SA
4
/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
/BW2
/BW3
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
6
/K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
7
/BW1
/BW0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
Top
Mid
Bottom
8
/R
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
D17
D16
Q16
Q15
D14
Q13
V
DDQ
D12
Q12
D11
D10
Q10
Q9
SA
10
NC
Q17
Q7
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
SA
C
QVLD
SA
QVLD
/C
NC
SA
ODT
(Top View)
R1Q3A7236
R1QA(G)A7236
R1QD(K)A7236
Notes: 1. Address expansion order for future higher density SRAMs: 10A
2. NC pins can be left floating or connected to 0V
V
DDQ
.
2A
7A
5B.
R1Q3A7218
(Top) /
R1QA(G)A7218
(Mid) /
R1QD(K)A7218
(Bottom)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
/CQ
NC
NC
NC
NC
NC
NC
/DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
3
SA
D9
D10
Q10
Q11
D12
Q13
V
DDQ
D14
Q14
D15
D16
Q16
Q17
SA
4
/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
/BW1
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
6
/K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
7
NC
/BW0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
/R
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
SA
C
QVLD
SA
QVLD
/C
NC
SA
ODT
(Top View)
Notes: 1. Address expansion order for future higher density SRAMs: 10A
2. NC pins can be left floating or connected to 0V
V
DDQ
.
2A
7A
5B.
Rev. 0.11 : 2013.01.15
R10DS0183EJ0011
PAGE:4
72---
R1QGA72 / R1QKA72 Series
Pin Arrangement
R1Q3A7209
(Top) /
R1QA(G)A7209
(Mid) /
R1QD(K)A7209
(Bottom)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
/CQ
NC
NC
NC
NC
NC
NC
/DOFF
NC
NC
NC
NC
NC
2
SA
NC
NC
D5
NC
NC
D6
V
REF
NC
NC
Q7
NC
D8
3
SA
NC
NC
NC
Q5
NC
Q6
V
DDQ
NC
NC
D7
NC
NC
4
/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
5
NC
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
6
/K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
7
NC
/BW
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
8
/R
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
Just Reference
10
SA
NC
NC
NC
D3
NC
NC
V
REF
Q2
NC
NC
NC
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
SA
SA
V
SS
NC
NC
C
QVLD
SA
SA
NC
D0
P
NC
NC
Q8
SA
SA
QVLD
/C
NC
SA
SA
SA
TMS
R
TDO TCK
SA
SA
SA
ODT
(Top View)
Notes: 1. Address expansion order for future higher density SRAMs: 10A
2A
7A
2. NC pins can be left floating or connected to 0V
V
DDQ
.
5B.
Rev. 0.11 : 2013.01.15
R10DS0183EJ0011
PAGE:5
