R5106N Series
Compact Watchdog Timer Equipped with Inhibit Pin with VD
The R5106N Series are CMOS-based system power ICs with a voltage detector (VD) and watchdog timer (WDT) integrated in a single
chip. R5106N monitors the power system of devices equipped with microprocessors and prevents system runaway with a reset
signal when a malfunction occurs. The output delay time of the VD and watchdog timeout period/reset time can be adjusted high
accuracy with an external capacitor. The R5106N is equipped with the function that inhibits clock monitoring of the WDT (INH).
FEATURES
•
Supply Current (I
SS
) ························Typ. 11μA (V
DD
=-V
DET
+0.5V,
Clock pulse input)
•
Operating Voltage (V
DD
)··················0.9V to 6.0V
(VD Section)
•
Detector Threshold Range (-V
DET
) ···1.5V to 5.5V (internally fixed)
•
Detector Threshold Accuracy ··········± 1%
•
Temp. coeff. of Detector Threshold ···Typ.
±
100ppm/°C
•
Output Delay Time (t
PLH
)················· Typ. 370ms (C
T
=0.1μF)
•
Output Delay Time Accuracy ··········
±
16% (-40°C
<
Topt
<
105°C)
=
=
(WDT Section)
•
Watchdog Timeout Period (t
WD
)······ Typ. 310ms (C
T
=0.1μF)
•
Reset Hold Time of WDT (t
WR
) ······· Typ. 34ms (C
T
=0.1μF)
•
Watchdog Timeout Period Accuracy ····
±
33% (-40°C
<
Topt
<
105°C)
=
=
•
Able to stop watchdog timer ··········· Inhibit (INH) Pin
•
Package ········································· SOT-23-6
(The above shows specification at Topt=25
°
C. Design assurance value at -40
°
C
<
Topt
<
105
°
C is also available. For details, please refer to the datasheet.)
=
=
BLOCK DIAGRAMS
R5106Nxx1A
(Nch. open drain output)
V
DD
3
SW1
V
DD
3
SW1
TYPICAL APPLICATION
R5106Nxx1C
(CMOS output)
Power Supply
R
Microprocessor
V
DD
3
V
DD
Vref2
Vref1
Vref2
Vref1
RESETB
4
R5106Nxx1A
1
Series
SCK
RESET
I/O
C
T
6
SW2
WATCHDOG
TIMER
CLOCK
DETECTOR
5 GND
1 SCK
C
T
6
SW2
WATCHDOG
TIMER
CLOCK
DETECTOR
5 GND
1 SCK
SW
2
INH
GND
C
T
6
C
T
5
RESETB 4
2 INH
RESETB 4
2 INH
SELECTION GUIDE
Package
SOT-23-6
Quantity per Reel
3,000 pcs
Part No.
R5106N.xx.1.
∗
-TR-F
.xx.
: Specify the detector threshold within the range 1.5V (.15.) to 5.5V (.55.)
in 0.1V steps.
.∗
: Select the output type from (.A.) Nch. open drain or (.C.) CMOS.
PACKAGE (Top View)
SOT-23-6
6
5
4
TIMING CHART
V
DD
+V
DET
-V
DET
V
INH
1
2
3
t
WD
t
PLH
t
WDI
1
2
3
4
5
6
SCK
INH
V
DD
RESETB
GND
C
T
Watchdog timer clock input pin
Inhibit pin
Power supply pin
Output pin for Reset "L" signal
Ground pin
Ext. Cap. pin for setting reset and
watchdog timeout period of WDT
and output delay time of VD
V
ref2H
V
CT
V
ref2L
t
PHL
V
SCK
t
PLH
t
WR
V
RESETB
APPLICATION
•
Monitoring of the power system of devices equipped with microprocessors
∗t
PHL
: Output delay time
∗t
WDI
: t
WD
/10 (SCK pulses input during this period are ignored.)
No.EK-169-091101
CMOS Microprocessor Supervisory
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