Datasheet
R8C/M13B Group
RENESAS MCU
R01DS0005EJ0200
Rev.2.00
Mar 19, 2012
1.
1.1
Overview
Features
The R8C/M13B Group of single-chip microcontrollers (MCUs) incorporates the R8C CPU core, which provides
sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, the CPU core is capable of
executing instructions at high speed. In addition, it features a multiplier for high-speed arithmetic processing.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs are
designed to maximize EMI/EMS performance.
Integration of many peripheral functions on the same chip, including multifunction timer and serial interface,
reduces the number of system components.
The R8C/M13B Group includes data flash (1 KB × 2 blocks).
1.1.1
Applications
Home appliances, office equipment, audio equipment, consumer products, etc.
R01DS0005EJ0200 Rev.2.00
Mar 19, 2012
Page 1 of 48
R8C/M13B Group
1. Overview
1.1.2
Specifications
Tables 1.1 and 1.2 outline the Specifications.
Table 1.1
Item
CPU
Specifications (1)
Function
Central processing
unit
Description
R8C CPU core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 2.7 V to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 1.8 V to 5.5 V)
• Multiplier: 16 bits × 16 bits
→
32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits
→
32 bits
• Operating mode: Single-chip mode (address space: 1 Mbyte)
See
Table 1.3 Product List.
• Hardware reset by RESET
• Power-on reset
• Watchdog timer reset
• Software reset
• Reset by voltage detection 0
Voltage detection with two check points:
Voltage detection 0, voltage detection 1 (detection levels selectable)
• 14 bits × 1 (with prescaler)
• Reset start function selectable
• Count source protection function selectable
• Periodic timer function selectable
• 4 circuits: XIN clock oscillation circuit, XCIN clock oscillation circuit,
high-speed on-chip oscillator (with frequency adjustment function),
low-speed on-chip oscillator
• Oscillation stop detection: XIN clock oscillation stop detection function
• Clock frequency divider circuit integrated
• Standard operating mode
• Wait mode (CPU stopped, peripheral functions in operation)
• Stop mode (CPU and peripheral functions stopped)
• Number of interrupt vectors: 69
• External interrupt inputs: 8 (INT × 4, key input × 4)
• Priority levels: 2
• CMOS I/O: 29 (pull-up resistor selectable)
• High-current drive ports: 8
16 bits × 1
Timer mode, pulse output mode (output level inverted every period),
event counter mode, pulse width measurement mode, pulse period
measurement mode
8 bits × 1 (with 8-bit prescaler) or 16 bits × 1 (selectable)
Timer mode, programmable waveform generation mode (PWM output),
programmable one-shot generation mode, programmable wait one-shot
generation mode
16 bits × 1 (with 4 capture/compare registers)
Timer mode (output compare function, input capture function),
PWM mode (3 outputs), PWM2 mode (1 PWM output)
8 bits × 1
Interval mode, pulse output mode, output compare mode
8 bits × 1
Real-time clock mode, compare match timer mode
Clock synchronous serial I/O. Also used for asynchronous serial I/O.
• Synchronous serial communication unit (SSU) × 1 channel
• I
2
C bus interface × 1 channel
Memory
Reset sources
ROM, RAM,
data flash
Voltage
Voltage detection
detection
circuit
Watchdog timer
Clock
Clock generation
circuits
Power control
Interrupts
I/O ports
Timer
Programmable I/O
ports
Timer RJ2
Timer RB2
Timer RC
Timer RK
Timer RE2
UART0
UART1
Clock synchronous serial interface
Serial
interface
R01DS0005EJ0200 Rev.2.00
Mar 19, 2012
Page 2 of 48
R8C/M13B Group
1. Overview
Table 1.2
Item
IrDA interface
A/D converter
Comparator B
Flash memory
Specifications (2)
Function
Description
1 channel (UART0 and UART1 can be switched)
• Resolution: 10 bits × 8 channels
• Sample and hold function, sweep mode
2 circuits
• Program/erase voltage for program ROM: VCC = 1.8 V to 5.5 V
• Program/erase voltage for data flash: VCC = 1.8 V to 5.5 V
• Program/erase endurance:10,000 times (data flash)
10,000 times (program ROM)
• Program security: ID code check, protection enabled by lock bit
• Debug functions: On-chip debug, on-board flash rewrite function
f(XIN) = 20 MHz (VCC = 2.7 V to 5.5 V)
f(XIN) = 5 MHz (VCC = 1.8 V to 5.5 V)
-20
°C
to 85
°C
(N version)
-40
°C
to 85
°C
(D version)
(1)
32-pin LQFP: [Package code] PLQP0032GB-A
Operating frequency/
Power supply voltage
Temperature range
Package
Note:
1. Specify the D version if its functions are to be used.
R01DS0005EJ0200 Rev.2.00
Mar 19, 2012
Page 3 of 48
R8C/M13B Group
1. Overview
1.2
Product List
Table 1.3 lists the Product List. Figure 1.1 shows the Product Part Number Structure.
Table 1.3
Product List
Internal ROM Capacity
Program ROM
Data Flash
4 Kbytes
1 Kbyte × 2
8 Kbytes
1 Kbyte × 2
16 Kbytes
1 Kbyte × 2
4 Kbytes
1 Kbyte × 2
8 Kbytes
1 Kbyte × 2
16 Kbytes
1 Kbyte × 2
Internal RAM
Capacity
384 bytes
512 bytes
1 Kbyte
384 bytes
512 bytes
1 Kbyte
Current of Mar 2012
Package Type
Remarks
Part No.
R5F2M131BNFP
R5F2M132BNFP
R5F2M134BNFP
R5F2M131BDFP
R5F2M132BDFP
R5F2M134BDFP
PLQP0032GB-A N version
D version
Part No. R 5 F 2MX X X B N FP
Package type:
FP: PLQP0032GB-A
Classification
N: Operating ambient temperature -20 °C to 85 °C
D: Operating ambient temperature -40 °C to 85 °C
ROM capacity
1: 4 KB
2: 8 KB
4: 16 KB
Number of pins
3: 32 pins
R8C/MXXB Group
R8C/Mx Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.1
Product Part Number Structure
R01DS0005EJ0200 Rev.2.00
Mar 19, 2012
Page 4 of 48
R8C/M13B Group
1. Overview
1.3
Block Diagram
Figure 1.2 shows the Block Diagram.
8
8
3
5
4
1
I/O ports
Peripheral functions
Timers
Port P0
Port P1
Port P2
Port P3
Port P4
Port PA
UART
(Clock synchronous serial I/O
Clock asynchronous serial I/O)
×
2
Timer RJ2 (16 bits
×
1)
Timer RB2 (8 bits
×
1
or 16 bits
×
1)
Timer RC (16 bits
×
1)
Timer RK (8 bits
×
1)
Timer RE2 (8 bits
×
1)
System clock generation
circuit
XIN-XOUT
XCIN-XCOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
Comparator B
Voltage detection circuit
Watchdog timer
(14 bits)
Clock synchronous serial
interface
Synchronous serial
communication unit (SSU)
I
2
C bus interface
A/D converter
(10 bits
×
8 channels)
IrDA Interface
R8C CPU core
R0H
R1H
R2
R3
A0
A1
FB
R0L
R1L
SB
USP
ISP
INTB
PC
FLG
Memory
ROM
(1)
RAM
(2)
Multiplier
Notes:
1. ROM size varies with the product.
2. RAM size varies with the product.
Figure 1.2
Block Diagram
R01DS0005EJ0200 Rev.2.00
Mar 19, 2012
Page 5 of 48
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