DatasheetDatasheet
RX62N Group, RX621 Group
Renesas MCUs
R01DS0052EJ0140
Rev.1.40
2014.07.16
100 MHz 32-bit RX MCU with FPU, 165 DMIPS, up to 512-Kbyte Flash,
Ethernet, USB 2.0 Full-Speed Host/Function/OTG, CAN, 12-bit ADC, TFT-LCD,
RTC, up to 14 communication channels
Features
■
32-bit RX CPU Core
Delivers 165 DMIPS at a maximum operating frequency of
100 MHz
Single Precision 32-bit IEEE-754 Floating Point
Accumulator: 32 × 32 to 64-bit result, one instruction
Mult/Divide Unit, 32 × 32 Multiply in one CPU clock for
multiple instructions
Interrupt response in as few as 5 CPU clock cycles
CISC-Harvard Architecture with 5-stage pipeline
Variable length instructions, ultra compact code
Supports the Memory Protection Unit (MPU)
Background JTAG debug plus high-speed trace
TFLGA85 7 × 7 mm, 0.65 mm pitch
TFLGA145 9 × 9 mm, 0.65 mm pitch
LFBGA176 13 × 13 mm, 0.8 mm pitch
LQFP100 14 × 14 mm, 0. 5mm pitch
LQFP144 20 × 20 mm, 0.5 mm pitch
■
Up to 14 Communication Interfaces
USB 2.0 Full-Speed interfaces with PHY (2 ch)
Supports Host/Function/OTG
10 endpoints for types: Control, Interrupt, Bulk, Isochronous
Ethernet MAC 10/100 Mbps, Half or Full Duplex Supported.
(1 ch)
Dedicated DMA with 2-Kbyte transmit and receive FIFOs.
RMII or MII interface to external PHY
CAN ISO11898-1, supports 32 mailboxes (1 ch)
SCI channels: Asynchronous, clock sync, smartcard, and 9-
bit modes (6 ch)
I
2
C interfaces up to 1 M bps, SMBus support (2 ch)
RSPI (2 ch)
■
Low Power Design and Architecture
2.7V to 3.6V operation from a single supply
480 µA/MHz Run Mode with all peripherals on
Deep Software Standby Mode with RTC
Four low power modes
■
Main Flash Memory, no Wait-State
100 MHz operation, 10 nsec read cycle
No wait states for read at full CPU speed
256K, 384K, 512K Byte size options
For Instructions or Operands
Programming from USB, SCI, JTAG, user code
■
External Address Space
Eight CS areas (8 × 16 Mbytes)
128-Mbyte SDRAM area
8-/16-/32-bit bus space selectable for each area
■
Data Flash Memory
Up to 32K Bytes with 30K Erase Cycles
Background Erase/Program does not stall CPU
■
TFT-LCD up to WQVGA resolution
■
Up to 20 Extended Function Timers
16-bit MTU2
Input capture, Output Compare, PWM output, phase count
mode (12 ch)
8-bit TMR (4 ch)
16-bit CMT (4 ch)
■
SRAM, no Wait-State
64K or 96K Byte size options
For Operands or Instructions
Back-up retention in Deep Software Standby Mode
■
DMA
Four fully programmable internal DMA channels
Two EXDMA channels for external-to-external transfers
Data Transfer Controller (DTC)
■
1-MHz ADC units with two combination choices
12-bit × 8 ch. unit with single sample/hold circuit
or (2) 10-bit × 4 ch units each with a sample/hold circuit
AD-converted value addition mode (12-bit A/D converter)
■
Reset and Supply Management
Power-On Reset (POR) monitor/generator
Low Voltage Detect (LVD) with precision setting
■
10-bit DAC, 2 channels
■
Up to 128 GPIO
5 V tolerant, Open-Drain, Internal Pull-up
■
System Clocking with Clock Monitoring
External crystal, 8 MHz to 14 MHz to Internal PLL
PLL source to system, USB, and Ethernet
Internal 125 kHz LOCO for IWDT
External crystal, 32 kHz for RTC
■
Operation Temp
–40°C to +85°C
■
Real Time Clock
Full calendar function, BCD format
■
Two Independent Watchdog Timers
125-kHz LOCO operation
R01DS0052EJ0140 Rev.1.40
2014.07.16
Page 1 of 150
RX62N Group, RX621 Group
1. Overview
1.
1.1
Overview
Outline of Specifications
Table 1.1
lists the specifications in outline, and
Table 1.2
lists the functions of products.
Table 1.1
Classification
CPU
Outline of Specifications (1 / 4)
Module/Function
CPU
Description
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
RAM
Data flash
MCU operating modes
Clock
Clock generation
circuit
Maximum operating frequency: 100 MHz
32-bit RX CPU
Minimum instruction execution time: One instruction per state (cycle of the system clock)
Address space: 4-Gbyte linear
Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Nine 32-bit registers
Accumulator: One 64-bit register
Basic instructions: 73
Floating-point instructions: 8
DSP instructions: 9
Addressing modes: 10
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32 x 32
64 bits
On-chip divider: 32 / 32
32 bits
Barrel shifter: 32 bits
Memory-protection unit (MPU)
Single precision (32-bit) floating point
Data types and floating-point exceptions in conformance with the IEEE754 standard
ROM capacity: 512 Kbytes (max.)
Two on-board programming modes
Boot mode (The user MAT is programmable via the SCI and USB.)
User program mode
Parallel programmer mode (for off-board programming)
FPU
Memory
ROM
RAM capacity: 96 Kbytes (max.)
Data flash capacity: 32 Kbytes
·
·
·
·
·
·
Single-chip mode, on-chip ROM enabled expansion mode, and on-chip ROM disabled
expansion mode (software switching)
Two circuits: Main clock oscillator and subclock oscillator
Internal oscillator: Low-speed on-chip oscillator
Structure of a PLL frequency synthesizer and frequency divider for selectable operating
frequency
Oscillation stoppage detection
Independent frequency-division and multiplication settings for the system clock (ICLK),
peripheral module clock (PCLK), and external bus clock (BCLK)
The CPU and other bus masters run in synchronization with the system
clock (ICLK): 8 to 100 MHz
Peripheral modules run in synchronization with the peripheral module
clock (PCLK): 8 to 50 MHz
Devices connected to the external bus run in synchronization with the external bus
clock (BCLK pin): 8 to 50 MHz*
1
Pin reset, power-on reset, voltage-monitoring reset, watchdog timer reset, independent
watchdog timer reset, and deep software standby reset
When the voltage on VCC falls below the voltage detection level (Vdet), an internal reset
or internal interrupt is generated.
Module stop function
Four low power consumption modes
Sleep mode, all-module clock stop mode, software standby mode, and deep software
standby mode
·
Reset
Voltage detection circuit
Low power
consumption
Low power
consumption
facilities
·
·
·
·
R01DS0052EJ0140 Rev.1.40
2014.07.16
Page 2 of 150
RX62N Group, RX621 Group
Table 1.1
Classification
Interrupt
1. Overview
Outline of Specifications (2 / 4)
Module/Function
Interrupt control unit
Description
·
·
·
·
·
·
·
Peripheral function interrupts: 146 sources
External interrupts: 16 (pins IRQ0 to IRQ15)
Non-maskable interrupts: 3 (the NMI pin, oscillation stop detection interrupt, and voltage-
monitoring interrupt)
Sixteen levels specifiable for the order of priority
Two breakpoint channels
Address breaks in fetch cycles are specifiable (enabling ROM correction)
The external address space can be divided into nine areas (CS0 to CS7, SDCS), each
with independent control of access settings.
Capacity of each area: 16 Mbytes (CS0 to CS7), 128 Mbytes (SDCS)
A chip-select signal (CS0# to CS7#, SDCS#) can be output for each area.
Each area is specifiable as an 8-, 16-, or 32-bit bus space (however, only 176-pin
versions support 32-bit bus spaces).
The data arrangement in each area is selectable as little or big endian (only for data).
SDRAM interface connectable
Bus format: Separate buses
Wait control
Write buffer facility
4 channels
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Software trigger, external interrupts, and interrupt requests from
peripheral functions
2 channels
Four transfer modes: Normal transfer, repeat transfer, block transfer, and cluster transfer
Single-address transfer enabled with the EDACK signal
Capable of direct data transfer to TFT LCD panels
Activation sources: Software trigger, external DMA transfer requests (EDREQ), and
interrupt requests from peripheral functions
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Software trigger, external interrupts and interrupt requests from
peripheral functions
I/O ports for the 176-pin LFBGA/145-pin TFLGA/144-pin LQFP/100-pin LQFP/85-pin
TFLGA
I/O pins: 126/103/103/72/58
Input pins: 2/2/2/2/2
Pull-up resistors: 56/44/44/40/28
Open-drain outputs: 35/33/33/27/23
5-V tolerance: 11/11/11/7/6
(16 bits x 6 channels) x 2 units
Time bases for the 12 16-bit timer channels can be provided via up to 32 pulse-input/
output lines and six pulse-input lines
Select from among eight counter-input clock signals for each channel (PCLK/1, PCLK/4,
PCLK/16, PCLK/64, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than channel 5, for
which only four signals are available.
Input capture function
21 output compare/input capture registers
Pulse output mode
Complementary PWM output mode
Reset synchronous PWM mode
Phase-counting mode
Generation of triggers for A/D converter conversion
Controls the high-impedance state of the MTU’s waveform output pins
User break controller
(as an optional
function)
External bus extension
DMA
DMA controller
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
EXDMA controller
Data transfer
controller
I/O ports
Programmable I/O
ports
Timers
Multi-function timer
pulse unit
Port output enable
R01DS0052EJ0140 Rev.1.40
2014.07.16
Page 3 of 150
RX62N Group, RX621 Group
Table 1.1
Classification
Timers
1. Overview
Outline of Specifications (3 / 4)
Module/Function
Programmable pulse
generator
8-bit timers
Description
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
(4 bits x 4 groups) x 2 units
Pulse output with the MTU output as a trigger
Maximum of 32-bit pulse output possible
(8 bits x 2 channels) x 2 units
Select from among seven internal clock signals (PCLK, PCLK/2, PCLK/8, PCLK/32,
PCLK/64, PCLK/1024, PCLK/8192) and one external clock signal
Capable of output of pulse trains with desired duty cycles or of PWM signals
The 2 channels of each unit can be cascaded to create a 16-bit timer
Generation of triggers for A/D converter conversion
Capable of generating baud-rate clocks for SCI5 and SCI6
(16 bits x 2 channels) x 2 units
Select from among four internal clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
8 bits x 1 channel
Select from among eight counter-input clock signals (PCLK/4, PCLK/64, PCLK/128,
PCLK/512, PCLK/2048, PCLK/8192, PCLK/32768, PCLK/131072)
Switchable between watchdog timer mode and interval timer mode
14 bits x 1 channel
Counter-input clock: Dedicated on-chip oscillator
Clock source: Subclock
Time/calendar
Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt
Input and output of Ethernet/IEEE 802.3 frames
Transfer at 10 or 100 Mbps
Full- and half-duplex modes
MII (Media Independent Interface) or RMII (Reduced Media Independent Interface) as
defined in IEEE 802.3u
Detection of Magic Packets
TM
*
or output of a "wake-on-LAN" signal (WOL)
Compliance with flow control as defined in IEEE 802.3x standards
Alleviation of CPU loads by the descriptor control method
Transmission FIFO: 2 Kbytes; Reception FIFO: 2 Kbytes
Includes a UDC (USB Device Controller) and transceiver for USB 2.0
Single port (176-pin products: two ports)
Compliance with the USB 2.0 specification
Transfer rate: Full speed (12 Mbps)
Self-power mode and bus power are selectable
OTG (On the Go) operation is possible
Incorporates 2 Kbytes of RAM as a transfer buffer
6 channels
Serial communications modes:
Asynchronous, clock synchronous, and smart-card interface
Multi-processor communications function
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Average transfer rate clock can be input from TMR timers for SCI5 and SCI6
Compare match
timer
Watchdog timer
Independent
watchdog timer
Realtime clock
Communication
function
Ethernet controller
Note:
*
Magic Packet
TM
is a registered trademark of Advanced Micro Devices, Inc.
DMA controller for
Ethernet controller
USB 2.0 host/
function module
Serial
communications
interfaces
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
R01DS0052EJ0140 Rev.1.40
2014.07.16
Page 4 of 150
RX62N Group, RX621 Group
Table 1.1
Classification
Communication
function
1. Overview
Outline of Specifications (4 / 4)
Module/Function
I
2
C bus interfaces
Description
·
·
·
·
·
·
2 channels (100-pin version: 1 channel)
Communications formats
I
2
C bus format/SMBus format
Master/slave selectable (For multi-master operation)
1 channel
32 mailboxes
2 channels
RSPI transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select),
and RSPI clock (RSPCK) signals enables serial transfer through SPI operation (four
lines) or clock-synchronous operation (three lines)
Capable of handling serial transfer as a master or slave
Data formats
Switching between MSB first and LSB first
The number of bits in each transfer can be changed to any number of bits from 8 to 16, or
to 20, 24, or 32 bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with each
frame having up to 32 bits)
Buffered structure
Double buffers for both transmission and reception
Max. transfer rate
In master mode: 18 Mbps
In slave mode: 6.25 Mbps
12 bits x 1 unit (1 unit x 8 channels) or 10 bits x 2 units (2 units x 4 channels);
12- and 10-bit A/D converters can be exclusively used.
10- or 12-bit resolution
Conversion time: 1.0
s
per channel (in operation with PCLK at 50 MHz)
Two operating modes
Single mode
Scan mode (one-cycle scan mode or continuous scan mode)
Sample-and-hold function
Three ways to start A/D conversion
Conversion can be started by software, a conversion start trigger from a timer (MTU or
TMR), or an external trigger signal.
Self-diagnostic functions
2 channels (1 channel for 100-pin products)
10-bit resolution
Output voltage: 0 V to VREFH
CRC code generation for arbitrary amounts of data in 8-bit units
Select any of three generating polynomials:
X
8
+ X
2
+ X + 1, X
16
+ X
15
+ X
2
+ 1, or X
16
+ X
12
+ X
5
+ 1.
Generation of CRC codes for use with LSB-first or MSB-first communications is
selectable.
CAN module
Serial peripheral
interfaces
·
·
·
·
12-bit A/D converter
10-bit A/D converter
·
·
·
·
·
·
·
·
·
·
·
·
·
D/A converter
CRC calculator
Operating frequency
Power supply voltage
Operating temperature
Package
8 to 100 MHz
VCC = PLLVCC = AVCC = 2.7 to 3.6V, VREFH = 2.7 to AVCC
40
to +85C
176-pin LFBGA (PLBG0176GA-A), 145-pin TFLGA (PTLG0145JB-A),
144-pin LQFP (PLQP0144KA-A), 100-pin LQFP (PLQP0100KB-A)*
2
85-pin TFLGA (PTLG0085JA-A)*
2,
*
3
Note 1. For products in the 100-pin LQFP and 85-pin TFLGA, the synchronizing frequency is 8 to 25 MHz.
Note 2. The 100-pin LQFP and 85-pin TFLGA do not support the SDRAM area controller and EXDMA controller.
Note 3. The 85-pin TFLGA does not support the port-output enabling.
R01DS0052EJ0140 Rev.1.40
2014.07.16
Page 5 of 150
