Features
RX63N Group, RX631 Group
Renesas MCUs
100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS, up to 2-MB flash
memory, various communications interfaces including Ethernet MAC,
full-speed USB 2.0 host/function/OTG interface, CAN, 10- & 12-bit A/D
converters, RTC
R01DS0098EJ0180
Rev.1.80
May 13, 2014
Features
RX63N Group products incorporate an Ethernet controller while
RX631 Group products do not.
■
32-bit RX CPU core
Max. operating frequency: 100 MHz
Capable of 165 DMIPS in operation at 100 MHz
Single precision 32-bit IEEE-754 floating point
Two types of multiply-and-accumulation unit (between memories and
between registers)
32-bit multiplier (fastest instruction execution takes one CPU clock cycle)
Divider (fastest instruction execution takes two CPU clock cycles)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions: Ultra-compact code
Supports the memory protection unit (MPU)
JTAG and FINE (two-line) debugging interfaces
PLQP0176KB-A
PLQP0144KA-A
PLQP0100KB-A
PLQP0064KB-A
PLQP0048KB-A
24 × 24 mm, 0.5-mm pitch
20 × 20 mm, 0.5-mm pitch
14 × 14 mm, 0.5-mm pitch
10 × 10 mm, 0.5-mm pitch
7 × 7 mm, 0.5-mm pitch
PTLG0177KA-A 8 × 8 mm, 0.5-mm pitch
PTLG0145KA-A 7 × 7 mm, 0.5-mm pitch
PTLG0100JA-A 7 × 7 mm, 0.65-mm pitch
PTLG0064JA-A 6 × 6 mm, 0.65-mm pitch
PLBG0176GA-A 13 × 13mm, 0.8-mm pitch
■
Various communications interfaces
■
Low-power design and architecture
Operation from a single 2.7- to 3.6-V supply
Low power consumption: A product that supports all peripheral functions
draws only 500
μA/MHz.
RTC is capable of operation from a dedicated power supply (min. operating
voltage: 2.3 V).
Four low-power modes
Supports ROM-less versions and versions with up to 2 Mbytes of ROM
(ROMless/256 Kbytes/384 Kbytes/512 Kbytes: RX631 Group only)
100-MHz operation, 10-ns read cycle (no wait states)
768-Kbyte to 2-Mbyte capacities
User code is programmable by on-board or off-board programming
ROM-less or 32 Kbytes of ROM (reprogrammable up to 100,000 times)
Programming/erasing as background operations (BGOs)
64 Kbytes/128 Kbytes/192 Kbytes/256 Kbytes of SRAM
For instructions and operands
Can provide backup on deep software standby
DMAC: Four channels
DTC
EXDMAC: Two channels
Dedicated DMAC for the Ethernet controller: Single channel
■
On-chip main flash memory, no wait states
Ethernet MAC (1) (not in RX631 Group products)
Host/function or OTG controller (1) and function controller (1) with full-
speed USB 2.0 transfer
CAN (compliant with ISO11898-1), incorporating 32 mailboxes (up to 3
modules)
SCI with multiple functionalities (up to 13)
Choose from among asynchronous mode, clock-synchronous mode, smart-
card interface mode, simplified SPI, simplified I2C, and extended serial
mode.
I
2
C bus interface for transfer at up to 1 Mbps (up to 4)
RSPI for high-speed transfer (up to 3)
Parallel data capture unit (PDC) (1) (available for 512 Kbytes/384 Kbytes/
256 Kbytes flash memory with 177-pin, 176-pin, 145-pin, and 144-pin)
Buses for high-speed data transfer (max. operating frequency of 50 MHz)
8 CS areas (8 × 16 Mbytes)
Multiplexed bus or separate bus are selectable per area.
8-, 16-, or 32-bit bus space is selectable per area
Independent SDRAM area (128 Mbytes)
■
External address space
■
On-chip data flash memory
■
On-chip SRAM, no wait states
■
Up to 20 extended-function timers
■
DMA
16-bit MTU2: input capture, output compare, PWM waveform output,
phase-counting mode (6 channels)
16-bit TPU: input capture, output compare, phase-counting mode (12
channels)
8-bit TMR (4 channels)
16-bit compare-match timers (4 channels)
Up to 21 × 12-bit channels, and incorporating 1 sample-and-hold circuit
Up to 8 × 10-bit channels, and incorporating 1 sample-and-hold circuit
Addition of results of A/D conversion (in the 12-bit converter)
Self diagnosis (for the 10-bit converter)
■
A/D converter for 1-MHz Operation
■
Reset and supply management
Power-on reset (POR)
Low voltage detection (LVD) with voltage settings
External crystal oscillator or internal PLL for operation at 4 to 16 MHz
Internal 125-kHz LOCO and 50-MHz HOCO
125-kHz clocks for the IWDT
Adjustment functions (30 seconds, leap year, and error)
Time capture function
(for capturing times in response to event-signal input on external pins)
125-kHz LOCO clock operation
■
Clock functions
■
10-bit D/A converter: 2 channels
■
Temperature sensor for measuring temperature within
the chip
■DEU
AES encryption and decryption functions
128/192/256-bit key length
ECB/CBC mode
■
Real-time clock
■
Independent watchdog timer
■
Useful functions for IEC60730 compliance
■
Register write protection can protect values in
important registers against overwriting.
■
Up to 134 pins for general I/O ports
■
Unique ID
5-V tolerance, open drain, input pull-up, switchable driving ability
16-byte ID code is provided for each chip (only for the G version)
D version: -40 to +85°C
G version: -40 to +105°C
Oscillation-stoppage detection, frequency measurement, CRC, IWDT, self-
diagnostic function for the A/D converter, etc.
■
Operating temp. range
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 1 of 208
RX63N Group, RX631 Group
1. Overview
1.
1.1
Overview
Outline of Specifications
Table 1.1
lists the specifications in outline, and table 1.2 gives a comparison of the functions of products in different
packages.
Table 1.1
is for products with the greatest number of functions, so numbers of peripheral modules and channels will
differ in accord with the package. For details, see
Table 1.2, Comparison of Functions for Different Packages in the
RX63N/RX631 Group.
Table 1.1
Classification
CPU
Outline of Specifications (1/6)
Module/Function
CPU
Description
Maximum operating frequency: 100 MHz
32-bit RX CPU
Minimum instruction execution time: One instruction per state (cycle of the system clock)
Address space: 4-Gbyte linear
Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Nine 32-bit registers
Accumulator: One 64-bit register
Basic instructions: 73
Floating-point instructions: 8
DSP instructions: 9
Addressing modes: 10
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32 x 32
64 bits
On-chip divider: 32 / 32
32 bits
Barrel shifter: 32 bits
Memory protection unit (MPU)
FPU
Memory
ROM
Single precision (32-bit) floating point
Data types and floating-point exceptions in conformance with the IEEE754 standard
Capacity: ROMless, 256 Kbytes, 384 Kbytes, 512 Kbytes, 768 Kbytes, 1 Mbyte, 1.5
Mbytes, 2 Mbytes
100 MHz, no-wait access
On-board programming: Four types
Off-board programming (parallel programmer mode) (for products with 100 pins or more)
Capacity: 64 Kbytes, 128 Kbytes, 192 Kbytes, 256 Kbytes
100 MHz, no-wait access
Capacity: 32 Kbytes
Programming/erasing: 100,000 times
Single-chip mode, on-chip ROM enabled expansion mode, and on-chip ROM disabled
expansion mode (software switching)
Main clock oscillator, subclock oscillator, low-speed/high-speed on-chip oscillator, PLL
frequency synthesizer, and IWDT-dedicated on-chip oscillator
Main-clock oscillation stoppage detection
Separate frequency-division and multiplication settings for the system clock (ICLK),
peripheral module clock (PCLK), FlashIF clock (FCLK) and external bus clock (BCLK)
The CPU and other bus masters run in synchronization with the system clock (ICLK):
Up to 100 MHz
Peripheral modules run in synchronization with the peripheral module clock (PCLK):
Up to 50 MHz
Flash IF run in synchronization with the flashIF clock (FCLK): Up to 50 MHz
Devices connected to the external bus run in synchronization with the external bus clock
(BCLK): Up to 50 MHz
RES# pin reset, power-on reset, voltage-monitoring reset, independent watchdog timer
reset, watchdog timer reset, deep software standby reset, and software reset
When the voltage on VCC passes the voltage detection level (Vdet), an internal reset or
internal interrupt is generated.
RAM
E2 data flash
MCU operating modes
Clock
Clock generation
circuit
Reset
Voltage detection circuit
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 2 of 208
RX63N Group, RX631 Group
Table 1.1
Classification
Low power
consumption
1. Overview
Outline of Specifications (2/6)
Module/Function
Low power
consumption facilities
Description
Module stop function
Four low power consumption modes
Sleep mode, all-module clock stop mode, software standby mode, and deep software
standby mode
Battery backup function
Peripheral function interrupts: 187 sources
External interrupts: 16 (pins IRQ0 to IRQ15)
Software interrupts: One source
Non-maskable interrupts: 6 sources
Sixteen levels specifiable for the order of priority
Interrupt
Interrupt controller
(ICUb)
External bus extension
The external address space can be divided into nine areas (CS0 to CS7, SDCS), each
with independent control of access settings.
Capacity of each area: 16 Mbytes (CS0 to CS7), 128 Mbytes (SDCS)
A chip-select signal (CS0# to CS7#, SDCS#) can be output for each area.
Each area is specifiable as an 8-, 16-, or 32-bit bus space.
The data arrangement in each area is selectable as little or big endian (only for data).
SDRAM interface connectable
Bus format: Separate bus, multiplex bus
Wait control
Write buffer facility
4 channels
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Software trigger, external interrupts, and interrupt requests from
peripheral functions
2 channels
Four transfer modes: Normal transfer, repeat transfer, block transfer, and cluster transfer
Single-address transfer enabled with the EDAKn signal
Capable of direct data transfer to TFT LCD panels
Activation sources: Software trigger, external DMA requests (EDREQn), and interrupt
requests from peripheral functions
DMA
DMA controller
(DMAC)
EXDMA controller
(EXDMACa)
Data transfer
controller (DTCa)
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: External interrupts and interrupt requests from peripheral functions
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May 13, 2014
Page 3 of 208
RX63N Group, RX631 Group
Table 1.1
Classification
I/O ports
1. Overview
Outline of Specifications (3/6)
Module/Function
General I/O ports
Description
I/O ports for the 177-pin TFLGA, 176-pin LFBGA and 176-pin LQFP
I/O pins: 133
Input pins: 1
Pull-up resistors: 133
Open-drain outputs: 133
5-V tolerance: 18
I/O ports for the 145-pin TFLGA and 144-pin LQFP
I/O pins: 111
Input pins: 1
Pull-up resistors: 111
Open-drain outputs: 111
5-V tolerance: 18
I/O ports for the 100-pin TFLGA (in the planning stage) and 100-pin LQFP
I/O pins: 78
Input pins: 1
Pull-up resistors: 78
Open-drain outputs: 78
5-V tolerance: 17
I/O ports for the 64-pin TFLGA
I/O pins: 39
Input pin: 1
Pull-up resistors: 39
Open-drain outputs: 39
5-V tolerance: 8
I/O ports for the 64-pin LQFP
I/O pins: 42
Input pin: 1
Pull-up resistors: 42
Open-drain outputs: 42
5-V tolerance: 8
8-bit port switching function
I/O ports for the 48-pin LQFP
I/O pins: 30
Input pin: 1
Pull-up resistors: 30
Open-drain outputs: 30
5-V tolerance: 6
8-bit port switching function
R01DS0098EJ0180 Rev.1.80
May 13, 2014
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RX63N Group, RX631 Group
Table 1.1
Classification
Timers
1. Overview
Outline of Specifications (4/6)
Module/Function
16-bit timer pulse unit
(TPUa)
Description
Multi-function timer
pulse unit 2 (MTU2a)
(16 bits x 6 channels) x 2 unit
Maximum of 16 pulse-input/output possible
Select from among seven or eight counter-input clock signals for each channel
Input capture/output compare function
Output of PWM waveforms in up to 15 phases in PWM mode
Buffered operation and phase-counting mode (two phase encoder input) depending on
the channel
Support for cascade-connected operation (32 bits x 2 channels)
PPG output trigger can be generated
Capable of generating conversion start triggers for the A/D converters
Signals from the input capture pins are input via a digital filter
Clock frequency measuring method
(16 bits x 6 channels) x 1 unit
Time bases for the 6 × 16-bit timer channels can be provided via up to sixteen pulse-input/
output lines and three pulse-input lines
Select from among eight counter-input clock signals for each channel (PCLK/1, PCLK/4,
PCLK/16, PCLK/64, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than channel 5, for
which only four signals are available.
Input capture function
21 output compare/input capture registers
Complementary PWM output mode
Reset synchronous PWM mode
Phase-counting mode
Generation of triggers for A/D converter conversion
Digital filter
Signals from the input capture pins are input via a digital filter
PPG output trigger can be generated
Clock frequency measuring function
The MTU or unit 0 TPU module can be used to monitor the main clock, subclock,
HOCO clock, LOCO clock, and PLL clock for abnormal frequencies.
Controls the high-impedance state of the MTU’s waveform output pins
(4 bits x 4 groups) x 2 units
Pulse output with the MTU2 or TPU output as a trigger
Maximum of 32 pulse-output possible
(8 bits x 2 channels) x 2 units
Select from among seven internal clock signals (PCLK/1, PCLK/2, PCLK/8, PCLK/32,
PCLK/64, PCLK/1024, PCLK/8192) and one external clock signal
Capable of output of pulse trains with desired duty cycles or of PWM signals
The 2 channels of each unit can be cascaded to create a 16-bit timer
Generation of triggers for A/D converter conversion
Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12
(16 bits x 2 channels) x 2 units
Select from among four internal clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
Clock sources: Main clock, subclock
Clock and calendar functions
Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt
Battery backup operation
Time-capture facility for three values
14 bits x 1 channel
Select from among 6 counter-input clock signals (PCLK/4, PCLK/64, PCLK/128, PCLK/
512, PCLK/2048, PCLK/8192)
14 bits x 1 channel
Counter-input clock: IWDT-dedicated on-chip oscillator
Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64, dedicated
clock/128, dedicated clock/256
Frequency measuring
method (MCK)
Port output enable 2
(POE2a)
Programmable pulse
generator (PPG)
8-bit timers (TMR)
Compare match timer
(CMT)
Realtime clock
(RTCa)
Watchdog timer
(WDTA)
Independent
watchdog timer
(IWDTa)
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May 13, 2014
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