Intel
PXA27x Processor Family
Memory Subsystem
Datasheet
Product Features
■
■
■
■
■
Device Architecture
— Flash die density: 128-, 256-Mbit
— LPSDRAM die density: 256-Mbit
— Flash + LPDRAM Combo (x16)
— Flash + Flash Combo (x32)
Device Voltage
— Core: V
CC
= 1.8 V (Typ)
— I/O: V
CCQ
= 1.8 V (Typ)
Device Packaging
— Ball count: 336 balls
— Area: 14x14 mm
— Height: 1.55 mm
SDRAM Architecture and Performance
— Clock rate: 104 MHz
— Four internal banks
— Burst Length: 1, 2, 4, 8, or full page
Quality and Reliability
— Extended Temp:
–
25
°C
to +85
°C
— Minimum 100 K flash block erase cycle
— 0.13
µm
ETOX VIII flash technology
■
■
■
Flash Architecture
— Read-While-Write or Erase
— Asymmetrical blocking structure
— 8-Mbit partition sizes (128-Mbit die)
— 16-Mbit partition sizes (256-Mbit die)
— 16-KWord parameter blocks (Bottom)
— 64-KWord main blocks
— 2-Kbit One-Time Programmable (OTP)
Protection Register
— Zero-latency block locking
— Absolute write protection with block lock
down using F-VPP and F-WP#
Flash Performance
— 85 ns initial access
— 25 ns async page-mode read
— 14 ns sync read (t
CHQV
)
— 52 MHz CLK
— Buffered Enhanced Factory Programming
(Buffered EFP): 5 µs/Byte (Typ)
— Buffered programming at 7 µs/Byte (Typ)
Flash Software
— Intel
FDI, Intel
PSM, and Intel
VFM
— Common Flash Interface (CFI)
— Basic/Extended Command Set
The Intel
®
PXA27x Processor Family Memory Subsystem is a stacked device combining high-
performance Intel StrataFlash
®
memory die with or without low-power SDRAM die in Intel
®
Stacked package. The flash memory features 1.8 V low-power operations with flexible multi-
partitions, dual operation Read-While-Write or Read-While-Erase, asynchronous and synchronous
reads up to 52 MHz on 0.13 µm ETOX™ VIII flash technology. The LPSDRAM memory features
1.8 V low-power operation up to 104 MHz. The PXA27x processor memory subsystem is stacked
on top of Intel
®
PXA27x Processor for an optimized small form-factor package solution for
cellular and PDA applications.
Notice:
This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
301855-001
July 2004
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL
®
PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Intel® PXA27x Processor Family Memory Subsystem
may contain design defects or errors known as errata which may cause the product to deviate
from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2004.
All rights reserved.
*Other names and brands may be claimed as the property of others.
2
Intel® PXA27x Processor Family Memory Subsystem
Datasheet
Contents
Contents
Part 1: Electrical, Mechanical, and Thermal Specifications (EMTS) ........ 7
1
Introduction
...............................................................................................................................9
1.1
1.2
1.3
Nomenclature .......................................................................................................................9
Acronyms ............................................................................................................................10
Conventions........................................................................................................................10
Intel StrataFlash® Memory Die...........................................................................................13
Device Description ..............................................................................................................14
Intel® PXA27x Processor Memory Subsystem Block Diagram ..........................................20
Package Mechanical Information........................................................................................23
Ballout Diagrams ................................................................................................................27
Signal Descriptions .............................................................................................................31
Absolute Maximum Ratings ................................................................................................35
Operating Conditions ..........................................................................................................36
Flash DC Current Characteristics .......................................................................................37
Flash DC Voltage Characteristics .......................................................................................38
LPSDRAM DC Characteristics ...........................................................................................39
AC Test Conditions.............................................................................................................41
Flash AC Read Specifications ............................................................................................42
Flash AC Write Specifications ............................................................................................47
Flash Program and Erase Characteristics ..........................................................................51
LPSDRAM Die Capacitance ...............................................................................................51
LPSDRAM AC Characteristics............................................................................................52
Flash Power-Up and Power-Down .....................................................................................55
Flash Output Disable ..........................................................................................................55
Flash Standby.....................................................................................................................55
Flash Reset.........................................................................................................................55
Flash Power Supply Decoupling .........................................................................................56
Flash Automatic Power Saving ...........................................................................................57
LPSDRAM Power-up Sequence and Initialization ..............................................................57
2
Device Overview
....................................................................................................................13
2.1
2.2
2.3
3
4
Package Information
............................................................................................................23
3.1
4.1
4.2
Ballout and Signal Descriptions
......................................................................................27
5
Maximum Ratings and Operating Conditions
...........................................................35
5.1
5.2
6
Electrical Specifications
.....................................................................................................37
6.1
6.2
6.3
7
AC Characteristics
................................................................................................................41
7.1
7.2
7.3
7.4
7.5
7.6
8
Power and Reset Specifications
.....................................................................................55
8.1
8.2
8.3
8.4
8.5
8.6
8.7
Datasheet
Intel® PXA27x Processor Family Memory Subsystem
3
Contents
Part 2: Flash Device Operations ............................................................ 59
9
Device Operations Overview
............................................................................................ 61
9.1
9.2
9.3
Flash and LPSDRAM Bus Operations................................................................................ 61
Flash Bus Operations ......................................................................................................... 64
Flash Command Definitions................................................................................................ 66
Flash Asynchronous Page-Mode Read .............................................................................. 69
Flash Synchronous Burst-Mode Read................................................................................ 70
10.2.1 Flash Burst Suspend ............................................................................................. 70
Flash Read Configuration Register..................................................................................... 70
10.3.1 Flash Read Mode .................................................................................................. 71
10.3.2 Flash Latency Count.............................................................................................. 72
10.3.3 Flash Burst Sequence ........................................................................................... 73
10.3.4 Flash Clock Edge................................................................................................... 74
10.3.5 Flash Burst Wrap ................................................................................................... 74
10.3.6 Flash Burst Length................................................................................................. 74
Flash Word Programming................................................................................................... 75
11.1.1 Flash Factory Word Programming......................................................................... 76
Flash Buffered Programming.............................................................................................. 76
Flash Buffered Enhanced Factory Programming................................................................ 77
11.3.1 Flash Buffered EFP Requirements and Considerations ........................................ 78
11.3.2 Flash Buffered EFP Setup Phase.......................................................................... 78
11.3.3 Flash Buffered EFP Program/Verify Phase ........................................................... 78
11.3.4 Flash Buffered EFP Exit Phase ............................................................................. 79
Flash Program Suspend ..................................................................................................... 79
Flash Program Resume...................................................................................................... 80
Flash Program Protection ................................................................................................... 80
Flash Block Erase............................................................................................................... 81
Flash Erase Suspend ......................................................................................................... 81
Flash Erase Resume .......................................................................................................... 82
Flash Erase Protection ....................................................................................................... 82
Flash Block Locking............................................................................................................ 83
13.1.1 Flash Lock Block.................................................................................................... 83
13.1.2 Flash Unlock Block ................................................................................................ 83
13.1.3 Flash Lock-Down Block ......................................................................................... 83
13.1.4 Flash Block Lock Status ........................................................................................ 84
13.1.5 Flash Block Locking During Suspend .................................................................... 84
Flash One-Time Programmable Protection Registers ........................................................ 85
13.2.1 Flash Reading of the Protection Registers ............................................................ 86
13.2.2 Flash Programming of the Protection Registers .................................................... 87
13.2.3 Flash Locking the Protection Registers ................................................................. 87
10
Flash Read Operations
....................................................................................................... 69
10.1
10.2
10.3
11
Flash Programming Operations
...................................................................................... 75
11.1
11.2
11.3
11.4
11.5
11.6
12
Flash Erase Operations
...................................................................................................... 81
12.1
12.2
12.3
12.4
13
Flash Security Modes
.......................................................................................................... 83
13.1
13.2
4
Datasheet
Contents
14
Flash Dual-Operation Considerations
..........................................................................89
14.1
14.2
Flash Partitioning ................................................................................................................89
Flash Read-While-Write Command Sequences .................................................................89
14.2.1 Simultaneous Flash Operation Details...................................................................90
14.2.2 Flash Write to Flash Asynchronous Read Transition.............................................90
14.2.3 Flash Write to Flash Synchronous Read Operation Transition..............................90
14.2.4 Flash Write with Clock Active.................................................................................90
14.2.5 Flash Read During Flash Buffered Programming ..................................................91
Simultaneous Flash Operation Restrictions........................................................................91
Flash Read Status Register ................................................................................................93
15.1.1 Flash Clear Status Register ...................................................................................94
Flash Read Device Identifier...............................................................................................95
CFI Query ...........................................................................................................................96
14.3
15
Special Flash Read States
.................................................................................................93
15.1
15.2
15.3
Part 3: LPSDRAM Operations ............................................................... 97
16
LSDRAM Register Definition
.............................................................................................99
16.1
16.2
Mode Register ....................................................................................................................99
LPSDRAM Extended Mode Register ................................................................................ 100
LPSDRAM No Operation / LPSDRAM Deselect............................................................... 101
LPSDRAM Active..............................................................................................................101
LPSDRAM Read Command ............................................................................................. 101
LPSDRAM Write Command ............................................................................................. 102
LPSDRAM Power-Down ...................................................................................................102
LPSDRAM Deep Power-Down .........................................................................................103
LPSDRAM Clock Suspend ............................................................................................... 103
LPSDRAM Precharge ....................................................................................................... 103
LPSDRAM Auto Precharge .............................................................................................. 103
LPSDRAM Concurrent Auto Precharge............................................................................ 103
LPSDRAM Burst Terminate .............................................................................................. 110
LPSDRAM Auto Refresh .................................................................................................. 110
LPSDRAM Self Refresh.................................................................................................... 111
17
LPSDRAM Command and Operation
........................................................................... 101
17.1
17.2
17.3
17.4
17.5
17.6
17.7
17.8
17.9
17.10
17.11
17.12
17.13
Appendix A
Appendix B
Appendix C
Appendix D
Appendix E
Flash Flowcharts
................................................................................................. 113
Common Flash Interface
.................................................................................. 121
Intel®
PXA27x Processor Memory Subsystem RAM Type ID
...........133
Additional Information
...................................................................................... 135
Ordering Introduction
........................................................................................137
Datasheet
Intel® PXA27x Processor Family Memory Subsystem
5
ARM技术
