Intel
®
Advanced+ Boot Block Flash
Memory (C3)
SCSP Family
Datasheet
Product Features
■
■
■
■
Flash Memory Plus SRAM
— Reduces Memory Board Space
Required, Simplifying PCB Design
Complexity
SCSP Technology
— Smallest Memory Subsystem Footprint
— Area : 8 x 10 mm for 16 Mbit (0.13 µm)
Flash + 2 Mbit or 4 Mbit SRAM
— Area : 8 x 12 mm for 32 Mbit (0.13 µm)
Flash + 4 Mbit or 8 Mbit SRAM
— Height : 1.20 mm for 16 Mbit (0.13 µm)
Flash + 2 Mbit or 4 Mbit SRAM, and 32
Mbit (0.13um) Flash + 8 Mbit SRAM
— Height : 1.40 mm for 32 Mbit (0.13 µm)
Flash + 4 Mbit SRAM
— This Family also includes 0.25 µm, 0.18
µm, and 0.13 µm technologies
Advanced SRAM Technology
— 70 ns Access Time
— Low Power Operation
— Low Voltage Data Retention Mode
Intel
®
Flash Data Integrator (FDI)
Software
— Real-Time Data Storage and Code
Execution in the Same Memory Device
— Full Flash File Manager Capability
■
■
■
■
Advanced+ Boot Block Flash Memory
—70 ns Access Time
—Instant, Individual Block Locking
—128 bit Protection Register
—12 V Production Programming
—Fast Program and Erase Suspend
—Extended Temperature –25 °C to +85 °C
Blocking Architecture
—Block Sizes for Code + Data Storage
—4-Kword Parameter Blocks
—64-Kbyte Main Blocks
—100,000 Erase Cycles per Block
Low Power Operation
—Asynchronous Read Current: 9 mA
(Flash)
—Standby Current: 7 µA (Flash)
—Automatic Power Saving Mode
Flash Technologies
—0.25 µm ETOX™ VI, 0.18 µm ETOX™
VII and 0.13 µm ETOX™ VIII Flash
Technologies
The Intel
®
Advanced+ Boot Block Flash Memory (C3) Stacked Chip Scale Package (SCSP)
device delivers a feature-rich solution for low-power applications. The C3 SCSP memory device
incorporates flash memory and static RAM in one package with low voltage capability to
achieve the smallest system memory solution form-factor together with high-speed, low-power
operations. The C3 SCSP memory device offers a protection register and flexible block locking
to enable next generation security capability. Combined with the Intel
®
Flash Data Integrator
(Intel
®
FDI) software, the C3 SCSP memory device provides a cost-effective, flexible, code plus
data storage solution.
Order Number: 252636, Revision: 004
26 Aug 2005
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL
®
PRODUCTS. EXCEPT AS PROVIDED IN INTEL’S TERMS
AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS
OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF INTEL PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO
FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER
INTELLECTUAL PROPERTY RIGHT.
Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by
estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The Intel
®
Advanced+ Boot Block Flash Memory (C3) may contain design defects or errors known as errata which may cause the product to deviate
from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at
http://www.intel.com.
Intel, the Intel logo, Intel StrataFlash, and ETOX are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States
and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2005, Intel Corporation. All rights reserved.
26 Aug 2005
2
Intel
®
Advanced+ Boot Block Flash Memory (C3) SCSP Family
Order Number: 252636, Revision: 004
Datasheet
C3 SCSP Flash Memory
Contents
1.0
Introduction....................................................................................................................................6
1.1
1.2
1.3
1.4
2.0
Document Conventions ........................................................................................................ 6
Product Overview .................................................................................................................6
Package Ballout .................................................................................................................... 8
Signal Definitions .................................................................................................................. 9
Principles of Operation
...............................................................................................................11
2.1
Bus Operation ..................................................................................................................... 11
2.1.1 Read ......................................................................................................................12
2.1.2 Output Disable ....................................................................................................... 12
2.1.3 Standby.................................................................................................................. 13
2.1.4 Flash Reset............................................................................................................ 13
2.1.5 Write ......................................................................................................................13
3.0
Flash Memory Modes of Operation............................................................................................14
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Read Array (FFh) ................................................................................................................ 14
Read Identifier (90h) ........................................................................................................... 14
Read Status Register (70h) ................................................................................................ 15
3.3.1 Clear Status Register (50h) ................................................................................... 16
CFI Query (98h) .................................................................................................................. 16
Word Program (40h/10h) .................................................................................................... 16
3.5.1 Suspending and Resuming Program (B0h/D0h)....................................................17
Block Erase (20h) ...............................................................................................................18
3.6.1 Suspending and Resuming Erase (B0h/D0h) ........................................................ 18
Block Locking......................................................................................................................20
3.7.1 Block Locking Operation Summary........................................................................ 21
3.7.2 Locked State .......................................................................................................... 21
3.7.3 Unlocked State ...................................................................................................... 21
3.7.4 Lock-Down State ................................................................................................... 21
3.7.5 Reading Lock Status for a Block............................................................................ 22
3.7.6 Locking Operation During Erase Suspend ............................................................ 22
3.7.7 Status Register Error Checking ............................................................................. 22
128 Bit Protection Register .................................................................................................23
3.8.1 Reading the Protection Register ............................................................................ 23
3.8.2 Programming the Protection Register (C0h).......................................................... 24
3.8.3 Locking the Protection Register ............................................................................. 24
3.8
4.0
Power and Reset Considerations
.............................................................................................. 25
4.1
4.2
Power-Up/Down Characteristics ......................................................................................... 25
Additional Flash Features ................................................................................................... 25
4.2.1 Improved 12 Volt Production Programming ...........................................................25
4.2.2 F-VPP
£ VPPLK
for Complete Protection .............................................................. 25
5.0
Electrical Specifications
............................................................................................................. 26
5.1
5.2
5.3
Absolute Maximum Ratings ................................................................................................ 26
Operating Conditions .......................................................................................................... 27
Capacitance ........................................................................................................................ 27
Datasheet
Intel
®
Advanced+ Boot Block Flash Memory (C3) SCSP Family
Order Number: 252636, Revision: 004
26 Aug 2005
3
C3 SCSP Flash Memory
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
6.0
7.0
DC Characteristics.............................................................................................................. 28
Flash AC Characteristics. ................................................................................................... 32
Flash AC Characteristics—Write Operations...................................................................... 33
Flash Erase and Program Timings(1)................................................................................. 34
Flash Reset Operations ...................................................................................................... 36
SRAM AC Characteristics—Read Operations.................................................................... 37
SRAM AC Characteristics—Write Operations .................................................................... 38
SRAM Data Retention Characteristics—Extended Temperature ....................................... 40
Migration Guide Information
...................................................................................................... 41
System Design Considerations..................................................................................................
41
7.1
Background......................................................................................................................... 41
7.1.1 Flash + SRAM Footprint Integration ...................................................................... 41
7.1.2 C3 Flash Memory Features ................................................................................... 42
Flash Control Considerations ............................................................................................. 42
7.2.1 F-RP# Connected to System Reset....................................................................... 42
7.2.2 F-VCC, F-VPP and F-RP# Transition .................................................................... 42
Noise Reduction ................................................................................................................. 43
Simultaneous Operation ..................................................................................................... 44
7.4.1 SRAM Operation during Flash “Busy” ................................................................... 45
7.4.2 Simultaneous Bus Operations ............................................................................... 45
Printed Circuit Board Notes ................................................................................................ 45
System Design Notes Summary......................................................................................... 45
7.2
7.3
7.4
7.5
7.6
A
B
Program/Erase Flowcharts ............................................................................................................ 46
CFI Query Structure ...................................................................................................................... 52
B.1
B.2
B.3
B.4
B.5
B.6
B.7
Query Structure Output....................................................................................................... 52
Query Structure Overview .................................................................................................. 53
Block Lock Status Register................................................................................................. 54
CFI Query Identification String............................................................................................ 54
System Interface Information.............................................................................................. 55
Device Geometry Definition ................................................................................................ 56
Intel-Specific Extended Query Table .................................................................................. 57
C
D
E
F
Word-Wide Memory Map Diagrams .............................................................................................. 59
Device ID Table ............................................................................................................................. 66
Protection Register Addressing ..................................................................................................... 67
Mechanical and Shipping Media Details........................................................................................ 68
F.8
F.9
Mechanical Specification .................................................................................................... 68
Media Information ............................................................................................................... 71
G
H
Additional Information.................................................................................................................... 73
Ordering Information...................................................................................................................... 74
26 Aug 2005
4
Intel
®
Advanced+ Boot Block Flash Memory (C3) SCSP Family
Order Number: 252636, Revision: 004
Datasheet
C3 SCSP Flash Memory
Revision History
Date of
Revision
02/11/03
01/29/04
03/05
26 Aug 2005
Version
-001
-002
-003
-004
Description
Initial release, Stacked Chip Scale Package
Minor text edits.
Updated Ordering Information figures and table in Appendix H.
Updated Ordering Information to add PF28F1602C3TD70.
Datasheet
Intel
®
Advanced+ Boot Block Flash Memory (C3) SCSP Family
Order Number: 252636, Revision: 004
26 Aug 2005
5
