RDC-19220 SERIES
16-BIT MONOLITHIC TRACKING
RESOLVER(/LVDT)-TO-DIGITAL CONVERTERS
AVAILABLE AS RADIATION HARDENED
IN RAD-PAK™ TECHNOLOGY BY
SPACE ELECTRONICS INC.
FEATURES
•
+5 Volt Only Option
•
Only Five External Passive
Components
DESCRIPTION
The RDC-19220 Series of converters
are low-cost, versatile, 16-bit monolith-
ic, state-of-the-art Resolver(/LVDT)-to-
Digital Converters. These single-chip
converters are available in small 40-pin
DDIP, or 44-pin J-Lead packages and
offer programmable features such as
resolution, bandwidth and velocity
output scaling.
Resolution programming allows
selection of 10-, 12-, 14-, or 16-bit,
with accuracies to 2.3 min. This fea-
ture combines the high tracking rate
of a 10-bit converter with the preci-
sion and low-speed velocity resolution
of a 16-bit converter in one package.
The velocity output (VEL) from the
RDC-19220 Series, which can be
used to replace a tachometer, is a 4 V
signal (3.5 V with the +5 V only
option) referenced to ground with a
linearity of 0.75% of output voltage.
The full scale value of VEL is set by
the user with a single resistor.
RDC-19220 Series converters are
available with operating temperature
ranges of 0° to +70°C, -40° to +85°C
and -55° to +125°C. Military pro-
cessing is available (consult factory).
•
Programmable:
- Resolution: 10-, 12-, 14-,
or 16-Bit
- Bandwidth: to 1200 Hz
- Tracking: to 2300 RPS
Input Modes
•
Differential Resolver and LVDT
•
Velocity Output Eliminates
Tachometer
APPLICATIONS
With its low cost, small size, high
accuracy and versatile performance,
the RDC-19220 Series converter is
ideal for use in modern high-perfor-
mance industrial and military control
systems. Typical applications include
motor control, radar antenna position-
ing, machine tool control, robotics,
and process control.
•
Built-In-Test (BIT) Output,
No 180° Hangup
•
Small Size: 40-Pin DDIP or
44-Pin J-Lead Package
•
-55° to +125°C Operating
Temperature Available
+REF -REF
BIT
-VSUM
SIN
-S
+S
COS
-C
+C
+5C
+CAP
-CAP
-5C
A GND
+5 V
GND
-5 V
-
+
A B
-5 V
INVERTER
16 BIT
UP/DOWN
COUNTER
E
DATA
LATCH
VCO
&
TIMING
-VCO
R
S
HYSTERESIS
INTEGRATOR
R
V
-
+
CONTROL
TRANSFORMER
GAIN
DEMODULATOR
R
1
C
BW
C
BW
10
R
B
VEL
R
C
INH
EM BIT 1 EL
THRU
BIT 16
A
B
CB
FIGURE 1. RDC-19220 SERIES BLOCK DIAGRAM
©
1990, 1999 Data Device Corporation
TABLE 1. RDC-19220 SPECIFICATIONS
These specifications apply over the rated power supply, temperature
and reference frequency ranges, and 10% signal amplitude variation
and harmonic distortion.
PARAMETER
RESOLUTION
ACCURACY
REPEATABILITY
DIFFERENTIAL LINEARITY
REFERENCE
Type
Voltage:
differential
single ended
overload
Frequency
Input Impedance
SIGNAL INPUT
Type
Voltage: operating
overload
Input impedance
DIGITAL INPUT/OUTPUT
Logic Type
Inputs
UNIT
Bits
Min
LSB
LSB
VALUE
10, 12, 14, or 16
±4, or ±2 + 1 LSB (note 3)
1 max
1 max in the 16th bit
(+REF, -REF)
Differential
V
P
-
P
V
P
V
Hz
Ohm
±10 max
±5 max
±25 continuous, 100 transient
DC to 40,000 (note 4)
10M min // 20 pf
TABLE 1. RDC-19220 SPECIFICATIONS (CONTD)
PARAMETER
DIGITAL INPUT/OUTPUT
(continued)
Outputs (continued)
Built-in-Test (BIT)
Logic 0 for BIT condition.
±100 LSBs of error typ. with a fil-
ter of 500 µS, or total Loss-of-
Signal (LOS)
50 pF +
Logic 0; 1 TTL load, 1.6 mA at
0.4 V max
Logic 1; 10 TTL loads, -0.4 mA
at 2.8 V min
Logic 0; 100 mV max driving
CMOS
Logic 1; +5 V supply minus 100
mV min driving CMOS High Z;
10 uA // 5 pF max
(at maximum bandwidth)
bits
rps
Hz
1/sec
2
1/sec
1/sec
1/sec
1/sec
deg/s
2
msec
10
1152
1200
5.7M
19.5
295k
2400
1200
2M
2
12
288
1200
5.7M
19.5
295k
2400
1200
500k
8
14
72
600
1.4M
4.9
295k
1200
600
30k
20
16
18
300
360k
1.2
295k
600
300
2k
50
UNIT
VALUE
Drive Capability
(+S, -S, SIN, +C, -C, COS)
Resolver, differential,
groundbased
Vrms 2 ±15%
V
±25 continuous
Ohm 10M min//10 pf.
TTL/CMOS compatible
Logic 0 = 0.8 V max.
Logic 1 = 2.0 V min.
Loading =10 µA max P.U. current
source to +5 V //5 pF max.
CMOS transient protected
Logic 0 inhibits; Data stable
within 0.3 µS
Logic 0 enables; Data stable
within 150 nS
Logic 1 = High Impedance
Data High Z within 100 nS
Mode
B
A
Resolution
resolver
0
0
10 bits
"
0
1
12 bits
"
1
0
14 bits
"
1
1
16 bits
LVDT - 5 V 0
8 bits
"
0 -5 V 10 bits
"
1 -5 V 12 bits
"
-5 V -5 V 14 bits
Inhibit (INH)
Enable Bits 1 to 8 (EM)
Enable Bits 9 to 16 (EL)
DYNAMIC
CHARACTERISTICS
Resolution
Tracking Rate (max)(note 4)
Bandwidth(Closed Loop)
(max) (note 4)
Ka
A1
A2
A
B
Acceleration (1 LSB lag)
Settling Time(179° step)
Resolution and Mode
Control(A & B)
(see notes 1 and 2.)
VELOCITY
CHARACTERISTICS
Polarity
Positive for increasing angle
Voltage Range(Full Scale)
V
±4 (at nominal ps)
Scale Factor Error
10 typ
20 max
%
Scale Factor TC
PPM/C 100 typ
200 max
Reversal Error
%
0.75 typ 1.3 max
Linearity
%
0.25 typ 0.50 max
Zero Offset
mv 5 typ
10 max
Zero Offset TC
30max
µV/C 15 typ
Load
kΩ
8 max
Noise
.125 min 2 max
(Vp/V)%
1 typ
POWER SUPPLIES
Nominal Voltage
Voltage Range
Max Volt. w/o Damage
Current
TEMPERATURE RANGE
Operating
-30X
-20X
-10X
Storage
plastic package
ceramic package
PHYSICAL
CHARACTERISTICS
Size: 40 pin DDIP
44 pin J-Lead
Weight:
40 pin DDIP
44 pin J-Lead
V
%
V
mA
(note 5)
+5
-5
± 5 +5, -20 (-4 V to -5.25 V)
+7
-7
14 typ, 22 max (each)
Outputs
Parallel Data (1-16)
Converter Busy (CB)
Zero Index
Notes:
(Zl)
10, 12, 14, or 16 parallel lines;
natural binary angle positive
logic (see TABLE 2)
0.25 to 0.75 µs positive pulse
leading edge initiates counter
update.
Logic 1 at all 0s (ENL to -5 V);
LSBs are enabled
°C
°C
°C
°C
°C
0 to +70
-40 to +85
-55 to +125
-40 to +85
-65 to +150
1. Unused data bits are set to logic “0.”
2. In LVDT mode, bit 16 is LSB for 14-bit resolution
or bit 12 is LSB for 10-bit resolution.
3. Accuracy in LVDT mode is 0.15% + 1 LSB of full scale.
4. See text, General Setup Considerations and Higher
Tracking Rates.
5. See text: General Setup Considerations for RDC19222.
in(mm) 2.0 x 0.6 x 0.2 (50.8 x 15.24 x 5.08)
in(mm) 0.690 square (17.526)
Plastic
oz(g) 0.21 (5.95)
oz(g) 0.08 (2.27)
Ceramic
0.24 (6.80)
0.065 (1.84)
2
THEORY OF OPERATION
The RDC-19220 Series of converters are single CMOS custom
monolithic chips. They are implemented using the latest IC tech-
nology which merges precision analog circuitry with digital logic
to form a complete, high-performance tracking resolver-to-digital
converter. For user flexibility and convenience, the converter
bandwidth, dynamics and velocity scaling are externally set with
passive components.
FIGURE 1 is the functional block diagram of the RDC-19220
Series. The converter operates with ±5 Vdc power supplies.
Analog signals are referenced to analog ground, which is at
ground potential. The converter is made up of two main sections;
a converter and a digital interface. The converter front-end con-
sists of sine and cosine differential input amplifiers. These inputs
are protected to ±25 V with 2 kΩ resistors and diode clamps to
the ±5 Vdc supplies. These amplifiers feed the high accuracy
Control Transformer (CT). Its other input is the 16-bit digital angle
φ.
Its output is an analog error angle, or difference angle,
between the two inputs. The CT performs the ratiometric trigono-
metric computation of SINθCOSφ - COSθSINφ = SIN(θ-φ) using
amplifiers, switches, logic and capacitors in precision ratios.
Note:
The transfer function of the CT is normally trigonometric,
but in LDVT-mode the transfer function is triangular (linear) and
could thereby convert any linear transducer output.
The converter accuracy is limited by the precision of the com-
puting elements in the CT. In these converters, ratioed capacitors
are used in the CT instead of the more conventional precision
ratioed resistors. Capacitors, used as computing elements with
op-amps, need to be sampled to eliminate voltage drifting.
Therefore, the circuits are sampled at a high rate (67 kHz) to
eliminate this drifting and at the same time to cancel out the op-
amp offsets.
The error processing is performed using the industry standard
technique for type II tracking R/D converters. The dc error is inte-
grated yielding a velocity voltage which in turn drives a voltage
controlled oscillator (VCO). This VCO is an incremental integra-
tor (constant voltage input to position rate output) which togeth-
er with the velocity integrator forms a type II servo feedback loop.
A lead in the frequency response is introduced to stabilize the
RB C
BW
loop and another lag at higher frequency is introduced to reduce
the gain and ripple at the carrier frequency and above. The set-
tings of the various error processor gains and break frequencies
are done with external resistors and capacitors so that the con-
verter loop dynamics can be easily controlled by the user.
TABLE 2. DIGITAL ANGLE OUTPUTS
BIT
1(MSB)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DEG/BIT
180
90
45
22.5
11.25
5.625
2.813
1.405
0.7031
0.3516
0.1758
0.0879
0.0439
0.0220
0.0110
0.0055
MIN/BIT
10800
5400
2700
1350
675
337.5
168.75
84.38
42.19
21.09
10.55
5.27
2.64
1.32
0.66
0.33
Note: EM enables the MSBs and EL enables the LSBs.
TRANSFER FUNCTION AND BODE PLOT
The dynamic performance of the converter can be determined
from its Transfer Function Block Diagrams and its Bode Plots
(open and closed loop). These are shown in FIGURES 2, 3, and
4.
The open loop transfer function is as follows:
Open Loop Transfer Function =
(
S +1
)
B
S
(
S +1
10B
)
A
2
2
where A is the gain coefficient and A
2
= A
1
A
2
and B is the frequency of lead compensation.
VEL
C
BW
/10
RS
-VSUM
VEL
-VCO
50 pf
C
VCO
CT
RESOLVER
INPUT
(θ)
+
GAIN
DEMOD
1
C
S
F
S
11 mV/LSB
±1.25 V
THRESHOLD
R
V
R1
VCO
-
16 BIT
UP/DOWN
COUNTER
H=1
DIGITAL
OUTPUT
(φ)
FIGURE 2. TRANSFER FUNCTION BLOCK DIAGRAM #1
3
The components of gain coefficient are error gradient, integrator
gain and VCO gain. These can be broken down as follows:
- Error Gradient = 0.011 volts per LSB (CT+Error Amp+Demod
with 2 Vrms input)
- Integrator gain =
- VCO Gain =
C
S
F
S
volts per second per volt
1.1C
BW
3) Resolver inputs and velocity output are referenced to A GND. This
pin should be connected to GND near the converter package. Digital
currents flowing through ground will not disturb the analog signals.
4) The BIT output which is active low is activated by an error of
approximately 100 LSBs. During normal operation for step inputs or
on power up, a large error can exist.
5) This device has several high impedence amplifier inputs (+C, -C, +S,
-S, -VCO and -VSUM). These nodes are sensitive to noise and cou-
pling components should be connected as close as possible.
6) Setup of bandwidth and velocity scaling for the optimized
critically damped case should proceed as follows:
- Select the desired f
BW
(closed loop), based on overall sys-
tem dynamics.
- Select fcarrier
≥
3.5 f
BW
- Compute R
v
1
LSBs per second per volt
1.25 R
v
C
vco
where: C
s
= 10 pF
F
s
= 67 kHz when R
s
= 30 kΩ
F
s
= 100 kHz when R
s
= 20 kΩ
F
s
= 134 kHz when R
s
= 15 kΩ
C
vco
= 50 pF
R
V
, R
B
, and C
BW
are selected by the user to set velocity scaling
and bandwidth.
{
= 55 kΩ x
For the converter max tracking rate value,
see the row indicated in TABLE 3.
}
Application max rate
GENERAL SETUP CONSIDERATIONS
DDC has external component selection software which consid-
ers all the criteria below, and in a simple fashion, asks the key
parameters (carrier frequency, resolution, bandwidth, and track-
ing rate) to derive the external component value.
The following recommendations should be considered when
installing the RDC-19220 Series R/D converters:
1) In setting the bandwidth (BW) and Tracking Rate (TR)
(selecting five external components), the system require-
ments need to be considered. For greatest noise immunity,
select the minimum BW and TR the system will allow.
2) Power supplies are ±5 V dc. For lowest noise performance
it is recommended that a 0.1 µF or larger cap be connected
from each supply to ground near the converter package.
8
- Compute C
BW
(pF) = 3.2 x F
S
(Hz) x 10
R
V x
(f
BW
)
2
- Where F
S
=
67 kHz for R
S
= 30 kΩ
100 kHz for R
S
= 20 kΩ
134 kHz for R
S
= 15 kΩ
0.9
C
BW
x f
BW
- Compute R
B
=
- Compute C
BW
10
Note: DDC has software available to perform the previous calcu-
lations. Contact DDC to request software or visit our website
at www.ddc-web.com to download software.
GAIN = 4
2A
OPEN LOOP
ERROR PROCESSOR
RESOLVER
INPUT
(θ)
+
-
CT
e
A1 S + 1
B
S
S +1
10B
-1
2d
b/o
ct
(CRITICALLY DAMPED)
VELOCITY
OUT
VCO
A
2
S
DIGITAL
POSITION
OUT (φ)
B
A
(B = A/2)
-6
db
/oc
t
ω
(rad/sec)
10B
GAIN = 0.4
f
BW
= BW (Hz) =
H=1
2A
π
CLOSED LOOP
2A
2 2A
ω
(rad/sec)
FIGURE 3. TRANSFER FUNCTION
BLOCK DIAGRAM #2
4
FIGURE 4. BODE PLOTS
7) Selecting a f
BW
that is too low relative to the maximum appli-
cation tracking rate can create a spin-around condition in
which the converter never settles. The relationship to insure
aganist spin-around is as follows (TABLE 3):
TABLE 3. TRACKING/BW RELATIONSHIP
RPS (MAX)/BW
RESOLUTION
1
0.45
0.25
0.125
10
12
14
16
For a 12-bit converter there are 2
12
or 4096 counts per rotation.
1,333,333/4096 = 325 rotations per second or 333,333 counts
per second per volt.
R
V
=
1
= 48k Ohms
(333,333 x 50 pF x 1.25)
8)
For RDC-19222:
This version is capable of +5V only operation. It accomplishes
this with a charge pump technique that inverts the +5V supply
for use as -5V, hence the +5V supply current doubles. The
built-in -5 V inverter can be used by connecting pin 2 to 26, pin
17 to 22, a 10 µF/10 Vdc capacitor from pin 23 (negative ter-
minal) to pin 25 (positive terminal), and a 47 µF/10 Vdc capac-
itor from -5 V to GND. The current drain from the +5 V supply
doubles. No external -5 V supply is needed.
When using the -5 V inverter, the max. tracking rate should be
scaled for a velocity output of 3.5 V max. Use the following
equation to determine tracking rate used in the formula on
page 4:
TR (required) x (4.0) = Tracking rate used in calculation
(3.5)
Note: When using the highest BW and Tracking Rates, using
the -5 V inverter is not recommended.
The maximum rate capability of the RDC-19220 is set by R
s
.
When R
s
= 30 kΩ it is nominally 1,333,333 counts/sec, which
equates to 325 rps (rotations per second). This is the absolute
maximum rate; it is recommended to only run at <90% of this rate
(as seen in TABLE 3), therefore the minumum Rv will be limited
to 55 kΩ. The converter maximum tracking rate can be increased
50% in the 16- and 14-bit modes and 100% in the 12- and 10-bit
modes by increasing the supply current from 12 to 15 mA (by
using an R
c
= 23 kΩ), and by increasing the sampling rate by
changing R
s
to 20 kΩ for 16- and 14-bit resolution or to 15 kΩ for
12- and 10-bit resolution (see TABLE 4).
The maximum carrier frequency can, in the same way, increase
from: 5 to 10 kHz in the 16-bit mode, 7 to 14 kHz in the 14-bit
mode,11 to 32 kHz in the 12-bit mode, and 20 to 40 kHz in the
10-bit mode (see TABLE 5).
The maximum tracking rate and carrier frequency for full perfor-
mance are set by the power supply current control resistor (R
c
)
per the following tables:
TABLE 4. MAX TRACKING RATE (MIN) IN
RPS
RC
Ω
(Ω)
30k** or open
23k
23k
RS
Ω
(Ω)
RESOLUTION
10
12
14
72
16
18
Depending on the res-
olution, select one of
the values from this
row, for use in convert-
er max tracking rate
formula. (See previous
page for formula.)
30k 1152 288
HIGHER TRACKING RATES AND CARRIER
FREQUENCIES.
Tracking rate (nominally 4 V) is limited by two factors: velocity
voltage saturation and maximum internal clock rate (nominally
1,333,333 Hz). An understanding of their interaction is essential
to extending performance.
The General Setup Considerations section makes note of the
selection of R
v
for the desired velocity scaling. R
v
is the input
resistor to an inverting integrator with a 50 pF nominal feedback
capacitor. When it integrates to -1.25 V, the converter counts up
1 LSB and when it integrates to +1.25 V, the converter counts
down 1 LSB. When a count is taken, a charge is dumped on the
capacitor; such that, the voltage on it changes 1.25 V in a direc-
tion to bring it to 0 V. The output counts per second per volt input
is therefore:
1
(Rv x 50 pF x 1.25)
As an example:
Calculate Rv for the maximum counting rate, at a VEL voltage
of 4 V.
20k 1728 432 108 27
15k 2304 576
*
*
* Not recommended.
** The use of a high quality thin-film resistor will provide better temperature
stability than leaving open.
TABLE 5. CARRIER FREQUENCY (MAX)
IN KHZ
RC
Ω
(Ω)
30k** or open
23k
23k
23k
RS
Ω
(Ω)
30k
30k
20k
15k
RESOLUTION
10
20
24
34
40
12
11
12
24
32
14
7
11
14
*
16
5
7
10
*
* Not recommended.
** The use of a high quality thin-film resistor will provide better temperature
stability than leaving open.
The carrier frequency should be 1/10, or less, of the sampling
frequency in order to have many samples per carrier cycle. The
converter will work with reduced quadrature rejection at a carri-
er frequency up to 1/4 the sampling frequency. Carrier frequen-
cy should be at least 3.5 times the BW in order to eliminate the
chance of jitter.
5
