RF25D
Tx ASIC for PCS Applications
The RF25D device includes the following functional blocks:
•
•
•
•
•
In-Phase and Quadrature (I/Q) modulator.
A Very High Frequency (VHF) Voltage Controlled Oscillator (VCO).
Intermediate Frequency (IF) Variable Gain Amplifier (VGA).
PCS upconverters with RF gain control.
PCS Power Amplifier (PA) drivers.
Features
•
PCS operation with high linearity
•
90 dB dynamic range from the VGA
•
Power saving operation in gated output
power mode
•
RF mixer gain option
•
Lower power consumption
•
Enable line for the entire chip
•
40-pin Land Grid Array (LGA) 6x6 mm
package
The RF25D Tx Application-Specific Integrated Circuit (ASIC) is a single-mode Personal
Communications System (PCS) transmitter intended to be used in Code Division
Multiple Access (CDMA) portable phones. The ASIC provides excellent RF performance
and is packaged in a low cost, high performance, 40-pin Land Grid Array (LGA),
6x6 mm package.
The device incorporates all the components to implement the completed transmitter
chain; from the In-Phase and Quadrature (I/Q) modulator to the PA driver amplifier,
except for external IF and RF SAW filters. The I/Q modulator receives differential inputs
from the baseband and upconverts to IF band. The IF VGA amplifies the IF signal with a
minimum dynamic range of 90 dB. The VGA also provides a compensation for gain
variation of off-chip components. After external IF filtering, the signal is upconverted to
RF PCS band frequency through a mixer. The mixer has an adjusted variable gain
option. With this option and VGA, the transmitted path’s gain can be redistributed. ACPR
and Signal-to-Noise (S/N) performance of the chip can be optimized. The RF signal is
filtered through an external filter and inputs to the drive amplifier.
There is a single on-chip Very High Frequency (VHF) Voltage Controlled Oscillator
(VCO), which operates with an external tank circuit and a varactor diode to generate the
Local Oscillator (LO) signal for I/Q modulator.
The Gain, ACPR and Noise Figure of each stage in the transmitter chip are optimized to
meet the system requirements per ANSI J-STD-018. Employing silicon bipolar
technology, the chip is designed for high performance with a high level integration and a
cost-effective RF solution for PCS mode phone application.
The device package and pinout are shown in Figure 1. A block diagram of the RF25D is
shown in Figure 2. A schematic diagram is shown in Figure 3.
Applications
•
PCS band phones
•
CDMA mode in the PCS band:
−
PCS (US)
−
PCS (Korean)
Data Sheet
Conexant – Preliminary
Proprietary Information
Doc. No. 101113A
August 3, 2000
RF25D
Tx ASIC
VCC_MIX
VGA_GC
MIX_IN+
MIX_IN-
LO_IN
VCO+
VCO-
33
40
39
38
37
36
35
34
32
VCC
31
30
29
28
27
26
25
24
23
22
21
NC
VCC_IF
RF_GC
VGA_OUT+
VGA_OUT-
VCC_LAST_DRV
DRV_ON
RF_OUT
VCC_BIAS
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
NC
PLL-
PLL+
NC
VCC_DIV
CHIP_ENA
VCC_DIFF_DRV
NC
MIX_OUT
NC
NC
POT
I+
I-
Q+
VCC_1ST_DRV
VCC_IQ_MOD
VCC
DRV_IN
Q-
C824
Figure 1. RF25D Tx ASIC Pinout – 40-Pin LGA 6x6 package
130.38 MHz
VGA_GC
DRIVER OUT
4
5
40
39
35
I Data
16
17
Q Data
19
20
I
÷2
Tx VGA
Q
Power
Management
8
RF_OUT
Lo Buf
34
33
29
To PLL
30
26
CHIP_ENA
36
LO_IN
3
RF_GC
23
15
260 MHz Tank
PCS SAW
C428
Figure 2. RF25D Tx ASIC Block Diagram
2
Conexant – Preliminary
Proprietary Information
101113A
August 3, 2000
Tx ASIC
RF25D
Technical Description
I/Q Modulator.
The I/Q modulator converts the incoming analog
baseband signals to balanced IF signals using the on-chip VHF
local oscillator. The I/Q modulator is internally connected to the
VGA, and its outputs are fully differential to reduce common
mode noise. The modulator is also designed to have very low
amplitude and phase imbalances.
VHF VCOs.
The on-chip Local Oscillator (LO) is a voltage
controlled oscillator (VCO). It has a frequency range of 100 to
640 MHz. With external tank circuits and a varactor diode, it
provides the LO signal to drive the I/Q modulator and the
prescalar of an external Phase Locked Loop (PLL) circuitry. The
oscillator typically operates at twice the IF frequency.
VGA.
The VGA is a differential amplifier that receives its signal
from the I/Q modulator, amplifies it, and sends it to the IF output
pins. An external filter should be attached to the IF output pins
for noise reduction. The VGA has a minimum dynamic range of
90 dB and a controlled voltage of 0.5 to 2.5 V. It also provides
compensation for any part-to-part and temperature gain
variation in the transmitted path.
Upconverters.
The PCS variable gain upconverter receives the
IF signal from the VGA after filtering through an external filter.
The upconverter uses an external LO controlled by an external
PLL to convert the IF signal to RF signal. With the variable mixer
gain and the VGA, the transmitted path’s gain can be
redistributed to yield an optimal ACPR and S/N performance.
The RF signal is sent to an output pin and then filtered by an
external RF filter before driver amplification.
PA Drivers.
The PA driver receives its input from the
upconverter after passing through an image rejected filter. The
driver amplifies the signal and sends it to an external PA.
The DRIVER_ON command is used during gated output power
mode to deactivate the drivers in periods of no transmission–A
feature intended for current saving. The POT_PCS (Pin 13),
accompanied by an external resistor, will alter the driver bias
point. The result is to change the driver gain and ACPR. A
Surface Acoustic Wave (SAW) filter for noise and spurious
rejection should be placed between the driver and the external
PA.
ESD Sensitivity
The RF25D is a Class 1 device. The following extreme
Electrostatic Discharge (ESD) precautions are required
according to the Human Body Model (HBM):
•
•
•
•
Protective outer garments.
Handle device in ESD safeguarded work area.
Transport device in ESD shielded containers.
Monitor and test all ESD protection equipment.
The HBM ESD withstand threshold value, with respect to
ground, is
±1.5
kV. The HBM ESD withstand threshold value,
with respect to VDD (the positive power supply terminal) is also
±1.5
kV.
Electrical and Mechanical Specifications
Included in this document are Tables 1 through 4 and Figures 1
through 4, which define the electrical and mechanical
specifications of the RF25D.
Table 1:
Table 2:
Table 3:
Table 4:
Figure 1:
Figure 2:
Figure 3 – 17:
Figure 18:
Figure 19:
Figure 20:
RF25D Pin Assignments and Signal
Descriptions
Absolute Maximum Ratings
Recommended Operating Conditions
RF25D Tx ASIC Electrical Specifications
RF25D Tx ASIC Pinout
RF25D Tx ASIC Block Diagram
Typical Functional Block Performance
RF25D Schematic Diagram
RF25D Tx ASIC Pin Package Dimensions
40-Pin LGA 6x6 mm Package
40-Pin LGA Tape and Reel Dimensions
101113A
August 3, 2000
Conexant – Preliminary
Proprietary Information
3
RF25D
Table 1. RF25D Pin Assignments and Signal Descriptions (1 of 2)
Pin #
1
2
3
NC
VCC_IF
RF_GC
Tx ASIC
Name
No connection.
Description
Supply voltage for the VGA, IF mux, and bias circuitry. A bypass capacitor(s) with a short trace
is required.
The gain control pin for both RF upconverters. A DC voltage of 1 to 2.5 V is needed to cover
the mixer RF range.
The output pin for the 130.38 MHz VGA. This is a balanced output. It should be connected to
an external bandpass filter for noise reduction. Requires an inductor choke to VCC IF on both
differential lines. Both outputs are open collectors.
Equivalent Circuit
4
VGA_OUT+
+
–
5
VGA_OUT-
Same as pin 4, except complementary output.
6
7
VCC_LAST_DRV
DRV_ON
Supply voltage for the PCS driver amplifier. A bypass capacitor(s) with a short trace is
required.
This is the driver control signal. When the pin is low, the driver is deactivated during no
transmission. During transmission the pin should be high to enable the driver. DRIVER_ON =
On to DRIVER_ON = Off can be used to provide a 33 dB step in cellular CDMA mode.
This is the output pin for the PCS RF signal. The pin is connected to the output of the PCS
driver amplifier. Impedance matching is required.
Supply voltage for biasing circuitry. A bypass capacitor(s) with a short trace is required.
No connection.
No connection.
Supply voltage. A bypass capacitor(s) with a short trace is required.
This pin is connected to an external resistor. The value of the resistor varies the bias current
of the PCS driver, which affects gain and ACPR. For PCS mode, the resistor range is 100 to
1.2 K ohms.
Supply voltage for the first amplifier in the PCS driver block. A bypass capacitor(s) with a short
trace is required.
This is the input pin for the PCS band driver. The input signal should pass through a SAW filter
before being connected to the driver. Impedance matching is required.
+
–
8
9
10
11
12
13
DRV_OUT
VCC_BIAS
NC
NC
VCC
POT_PCS
14
15
VCC_1ST_DRV
DRV_IN
Vcc
16
I+
The I/Q modulator baseband balanced input for the I channel. A typical 1.85 V DC bias is
required to both differential input pins.
+
–
17
I-
Same as pin 16, except complementary input.
18
VCC_IQ_MOD
Supply voltage for the I/Q modulator. A bypass capacitor(s) with a short trace is required.
4
Conexant – Preliminary
Proprietary Information
101113A
August 3, 2000
Tx ASIC
RF25D
Pin #
19
Q+
Name
Description
The I/Q modulator baseband balanced input for the Q channel. A DC bias has to be supplied
to the pin. A typical 1.85 DC bias is required to both differential input pins.
Equivalent Circuit
+
–
20
Q-
Same as pin 19, except complementary input.
21
22
23
NC
NC
MIX_OUT
No connection.
No connection.
This is the output pin for the PCS upconverter and needs impedance matching. The RF output
signal should be routed through an image rejection filter before being connected to the driver
input.
Vcc
24
25
26
27
28
29
NC
VCC_DIFF_DRV
CHIP_ENA
VCC_DIV
NC
PLL+
No connection.
Supply voltage for a differential amplifier in the upconverter block. A bypass capacitor(s) with a
short trace is required.
This is the IQ modulator, VGA, and upconverter enable signal. When the input is low, the chip
is disabled. When the input is high, the chip is enabled.
Supply voltage for the divider and VCO buffer. A bypass capacitor(s) with a short trace is
required.
No connection.
This is a balanced output pin for the VCO. This output goes to an external PLL that locks the
VCO frequency.
Vcc
Vcc
+
–
30
PLL-
Same as pin 29, except complementary input
31
32
33
NC
VCC
VCO-
No connection.
Supply voltage. A bypass capacitor(s) with a short trace is required.
This is a balanced input for the external VCO tank circuitry. The tank circuit values estimate the
frequency of oscillation (and the Q factor) of the LO. This tank circuit should contain a varacter
to directly frequency modulate the IF at the modulator output. The output frequency of the
VCO is a divided by 2 before applying to the I/Q modulator.
Same as pin 33, except a complementary input.
–
+
34
VCO+
101113A
August 3, 2000
Conexant – Preliminary
Proprietary Information
5
