®
RT8877C
Dual-Output PWM Controller for AMD SVI2 CPU Power
Supply
General Description
The RT8877C is a 4 + 2 phases PWM controller. Moreover,
it is compliant with AMD SVI2 Voltage Regulator
Specification to support both CPU core (VDD) and
Northbridge portion of the CPU (VDDNB). The RT8877C
features CCRCOT (Constant Current Ripple Constant On-
Time) with G-NAVP (Green-Native AVP), which is a
Richtek's proprietary topology. G-NAVP makes it an easy
setting controller to meet all AMD AVP (Active Voltage
Positioning) VDD/VDDNB requirements. The droop is
easily programmed by setting the DC gain of the error
amplifier. With proper compensation, the load transient
response can achieve optimized AVP performance. The
controller also uses the interface to issue VOTF Complete
and to send digitally encoded voltage and current values
for the VDD and VDDNB domains. It can operate in single
phase and diode emulation mode and reach up to 90%
efficiency in different modes according to different loading
conditions. The RT8877C provides special purpose offset
capabilities by pin setting. The RT8877C also provides
power good indication, over current indication (OCP_L)
and dual OCP mechanism for AMD SVI2 CPU core and
NB. It also features complete fault protection functions
including over voltage, under voltage and negative voltage.
Features
4/3/2/1-Phase (VDD) + 2/1/0-Phase (VDDNB) PWM
Controller
G-NAVP
TM
Topology
Support Dynamic Load Line and Zero Load Line
Diode Emulation Mode at Light Load Condition
SVI2 Interface to Comply AMD Power Management
Protocol
Build-in ADC for V
OUT
and I
OUT
Reporting
Immediate OV, UV and NV Protections and UVLO
Programmable Dual OCP Mechanism
0.5% DAC Accuracy
Fast Transient Response
Power Good Indicator
Over Current Indicator
52-Lead WQFN Package
RoHS Compliant and Halogen Free
Applications
AMD SVI2 CPU
Desktop Computer
Simplified Application Circuit
RT8877C
OCP_L
PWM1
PWM2
SVC
To CPU
SVD
SVT
PWM3
PWM4
PWMA1
PWMA2
RT9624A
RT9624A
RT9624A
RT9624A
RT9624A
RT9624A
MOSFET
MOSFET
MOSFET
MOSFET
MOSFET
MOSFET
V
VDD
V
VDDNB
Copyright
©
2012 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS8877C-00
November 2012
www.richtek.com
1
RT8877C
Ordering Information
RT8877C
Package Type
QW : WQFN-52L 6x6 (W-Type)
Lead Plating System
Z : ECO (Ecological Element with
Halogen Free and Pb free)
Note :
Richtek products are :
RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
Pin Configurations
(TOP VIEW)
PWM3
PWM2
PWM1
NC
NC
NC
DVD
NC
NC
NC
PWMA1
PWMA2
TONSETA
52 51 50 49 48 47 46 45 44 43 42 41 40
Marking Information
RT8877CZQW : Product Number
Copyright
©
2012 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
2
RGND
IMON
V064
IMONA
VDDIO
PWROK
SVC
SVD
SVT
OFS
OFSA
SET1
SET2
RT8877C
ZQW
YMDNN
YMDNN : Date Code
PWM4
TONSET
ISEN2P
ISEN2N
ISEN1N
ISEN1P
ISEN3P
ISEN3N
ISEN4N
ISEN4P
VSEN
FB
COMP
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20 21 22 23 24 25 26
53
39
38
37
36
35
34
GND
33
32
31
30
29
28
27
PGOOD
PGOODA
EN
ISENA1P
ISENA1N
ISENA2N
ISENA2P
VSENA
FBA
COMPA
IBIAS
VCC
OCP_L
WQFN-52L 6x6
DS8877C-00
November 2012
RT8877C
Functional Pin Description
Pin No.
1, 52, 51, 50
2
5, 4, 8, 9
6, 3, 7, 10
11
12
13
14
15
16
17
18
Pin Name
PWM4 to PWM1
TONSET
ISEN1N to ISEN4N
ISEN1P to ISEN4P
VSEN
FB
COMP
RGND
IMON
V064
IMONA
VDDIO
Pin Function
PWM Outputs for Channel 1, 2, 3 and 4 of VDD Controller.
VDD Controller On-Time Setting. Connect this pin to the converter input
voltage, Vin, through a resistor, RTON, to set the on-time of UGATE and
also the output voltage ripple of VDD controller.
Negative Current Sense Input of Channel 1, 2, 3 and 4 for VDD Controller.
Positive Current Sense Input of Channel 1, 2, 3 and 4 for VDD Controller.
VDD Controller Voltage Sense Input. This pin is connected to the terminal
of VDD controller output voltage.
Output Voltage Feedback Input of VDD Controller. This pin is the negative
input of the error amplifier for the VDD controller.
Error Amplifier Output Pin of the VDD Controller.
Return Ground of VDD and VDDNB Controller. This pin is the common
negative input of output voltage differential remote sense for VDD and
VDDNB controllers.
Current Monitor Output for the VDD Controller. This pin outputs a voltage
proportional to the output current.
Fixed 0.64V Reference Voltage Output. This voltage is only used to offset
the output voltage of IMON pin and IMONA pin. Connect a 0.47μF
capacitor from this pin to GND.
Current Monitor Output for the VDDNB Controller. This pin outputs a
voltage proportional to the output current.
Processor memory interface power rail and serves as the reference for
PWROK, SVD, SVC and SVT. This pin is used by the VR to reference the
SVI pins.
System Power Good Input. If PWROK is low, the SVI interface is disabled
and VR returns to BOOT-VID state with initial load line slope and initial
offset. If PWROK is high, the SVI interface is running and the DAC
decodes the received serial VID codes to determine the output voltage.
Serial VID Clock Input from Processor.
Serial VID Data input from Processor. This pin is a serial data line.
Serial VID Telemetry Input from VR. This pin is a push-pull output.
Over Clocking Offset Setting for the VDD Controller.
Over Clocking Special Purpose Offset Setting for the VDDNB Controller.
OCP_TDC threshold setting individually for VDD and VDDNB controllers
and also the internal ramp slew rate setting (RSET and RSETA)
individually for VDD and VDDNB controllers
Quick response threshold setting individually for VDD and VDDNB
controllers (QRTH and QRTHA) and also the OCP_TDC trigger delay time
setting for both controllers and over clocking offset enable setting.
Over Current Indicator for Dual OCP Mechanism. This pin is an open drain
output.
Controller Power Supply Input. Connect this pin to 5V with an 1μF or
greater ceramic capacitor for decoupling.
19
PWROK
20
21
22
23
24
25
SVC
SVD
SVT
OFS
OFSA
SET1
26
SET2
27
28
OCP_L
VCC
Copyright
©
2012 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS8877C-00
November 2012
www.richtek.com
3
RT8877C
Pin No.
29
30
31
32
33, 36
34, 35
37
38
39
Pin Name
IBIAS
COMPA
FBA
VSENA
ISENA2P,
ISENA1P
ISENA2N,
ISENA1N
EN
PGOODA
PGOOD
Pin Function
Internal Bias Current Setting. Connect only a 100kΩ resistor from this pin to
GND to generate bias current for internal circuit. Place this resistor as close
to IBIAS pin as possible.
Error Amplifier Output of the VDDNB Controller.
Output Voltage Feedback Input of VDDNB Controller. This pin is the negative
input of the error amplifier for the VDDNB controller.
VDDNB Controller Voltage Sense Input. This pin is connected to the terminal
of VDDNB controller output voltage.
Positive Current Sense Input of Channel 1 and 2 for VDDNB Controller.
Negative Current Sense Input of Channel 1 and 2 for VDDNB Controller.
Controller Enable pin. A logic high signal enables the controller.
Power Good Indicator for the VDDNB Controller. This pin is an open drain
output.
Power Good Indicator for the VDD Controller. This pin is an open drain
output.
VDDNB Controller On-Time Setting. Connect this pin to the converter input
voltage, Vin, through a resistor, RTONNB, to set the on-time of
UGATE_VDDNB and also the output voltage ripple of VDDNB controller.
PWM Output for Channel 1 and 2 of VDDNB Controller.
No Internal Connection.
External Driver Power Supply Input Voltage Detection Pin.
Ground. The exposed pad must be soldered to a large PCB and connected
to GND for maximum power dissipation.
40
41, 42
43, 44, 45,
47, 48, 49
46
53 (Exposed Pad)
TONSETA
PWMA2,
PWMA1
NC
DVD
GND
Copyright
©
2012 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
4
DS8877C-00
November 2012
RT8877C
Function Block Diagram
PWROK
VDDIO
SVD
SVC
SVT
PGOODA
PGOOD
VSEN
VSENA
OCP_L
OFSA
SET1
SET2
VCC
DVD
OFS
IMONI
IMONAI
EN
MUX
ADC
IBIAS
SVI2 Interface
Configuration Registers
Control Logic
From Control Logic
RGND
DAC
VSETA
ERROR
AMP
+
-
UVLO
GND
OFS/OFSA
Load Line
/Load Line A
RSET/RSETA
TONSETA
OCP Threshold
PWM
CMPA
QRA
TONA
PWMA1
TON
GENA
PWMA2
Loop Control
Protection Logic
Soft-Start & Slew
Rate Control
FBA
COMPA
ISENA1P
ISENA1N
Offset
Cancellation
+
+
-
Current mirror
+
x2
-
IBA1
V064
Current mirror
+
0.4
-
RSETA
Current Balance
Average
IMONAI
IBA1
OCP_TDCA,
OCP_SPIKEA
+
-
ISENA2P
ISENA2N
IMONA
From Control Logic
RGND
DAC
Soft-Start & Slew Rate
Control
+
x2
-
IBA2
IBA2
OCA
To Protection Logic
OV/UV/NV
PWM
CMP
QR
TON
TON
GEN
TONSET
PWM1
PWM2
PWM3
PWM4
VSENA
ERROR
AMP
VSET
+
-
FB
COMP
Offset
Cancellation
+
+
-
Current mirror
ISEN1P
ISEN1N
+
x1
-
IB1
+
0.4
-
Current mirror
ISEN2P
ISEN2N
+
x1
-
RSET
Current Balance
Average
IMONI
IB1
IB2
IB3
IB4
IB2
Current mirror
ISEN3P
ISEN3N
+
x1
-
IB3
Current mirror
ISEN4P
ISEN4N
+
x1
-
IB4
OCP_TDC,
OCP_SPIKE
+
-
OC
To Protection Logic
OV/UV/NV
VSEN
IMON V064
Copyright
©
2012 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS8877C-00
November 2012
www.richtek.com
5
嵌入式系统
