v5.3
RTAX-S/SL RadTolerant FPGAs
Radiation Performance
•
SEU-Hardened Registers Eliminate the Need for Triple-
Module Redundancy (TMR)
– Immune to Single-Event Upsets (SEU) to LET
TH
> 37
MeV-cm
2
/mg
– SEU Rate < 10
-10
Errors/Bit-Day in Worst-Case
Geosynchronous Orbit
Expected SRAM Upset Rate of <10
-10
Errors/Bit-Day with
Use of Error Detection and Correction (EDAC) IP (included)
with Integrated SRAM Scrubber
– Single-Bit Correction, Double-Bit Detection
– Variable-Rate Background Refreshing
Total Ionizing Dose Up to 300 krad (Si, Functional)
Single-Event Latch-Up Immunity (SEL) to LET
TH
> 117 MeV-
cm
2
/mg
TM1019 Test Data Available
Single Event Transient (SET) – No Anomalies up to 150 MHz
Leading-Edge Performance
•
•
•
•
High-Performance Embedded FIFOs
350+ MHz System Performance
500+ MHz Internal Performance
700 Mb/s LVDS Capable I/Os
•
Specifications
•
•
•
•
•
•
Up to 4 Million Equivalent System Gates or 500 k
Equivalent ASIC Gates
Up to 20,160 SEU-Hardened Flip-Flops
Up to 840 I/Os
Up to 540 kbits Embedded SRAM
Manufactured on Advanced 0.15
μm
CMOS Antifuse
Process Technology, 7 Layers of Metal
Electrostatic Discharge (ESD) is 2,000 V (HBM MIL-STD-883,
TM3015)
•
•
•
•
Processing Flows
•
•
•
B-Flow – MIL-STD-883B
E-Flow – Actel Extended Flow
EV-Flow – Class V Equivalent Flow Processing Consistent
with MIL-PRF 38535
Features
•
•
•
Single-Chip, Nonvolatile Solution
1.5 V Core Voltage for Low Power
Flexible, Multi-Standard I/Os:
– 1.5 V, 1.8 V, 2.5 V, 3.3 V Mixed Voltage Operation
– Bank-Selectable I/Os – 8 Banks per Chip
– Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3 V PCI
– JTAG Boundary Scan Testing (as per IEEE 1149.1)
– Differential I/O Standards: LVPECL and LVDS
– Voltage-Referenced I/O Standards: GTL+, HSTL Class 1,
SSTL2 Class 1 and 2, SSTL3 Class 1 and 2
– Hot-Swap Compliant with Cold-Sparing Support
(Except PCI)
Embedded Memory with Variable Aspect Ratio and
Organizations:
– Independent, Width-Configurable Read and Write Ports
– Programmable Embedded FIFO Control Logic
– ROM Emulation Capability
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Debug Capability
Prototyping Options
•
•
Commercial
Axcelerator
Devices
for
Functional
Verification
RTAX-S PROTO Devices with Same Functional and Timing
Characteristics as Flight Unit in a Non-Hermetic Package
•
RTAX-SL Low Power Option
•
Offers Approximately Half the Standby Current of the
Standard RTAX-S Device at Worst-Case Conditions
•
•
Table 1 •
RTAX-S/SL Family Product Profile
Device
Capacity
Equivalent System Gates
ASIC Gates
Modules
Register (R-cells)
Combinatorial (C-cells)
Flip-Flops (maximum)
Embedded RAM/FIFO (without EDAC)
Core RAM Blocks
Core RAM Bits (K = 1,024)
Clocks (segmentable)
Hardwired
Routed
I/Os
I/O Banks
User I/Os (maximum)
I/O Registers
Package
CCGA/LGA
CQFP
RTAX250S/SL
250,000
30,000
1,408
2,816
2,816
12
54 k
4
4
8
198
744
–
208, 352
RTAX1000S/SL
1,000,000
125,000
6,048
12,096
12,096
36
162 k
4
4
8
418
1,548
624
352
RTAX2000S/SL
2,000,000
250,000
10,752
21,504
21,504
64
288 k
4
4
8
684
2,052
624, 1152
256, 352
RTAX4000S
4,000,000
500,000
20,160
40,320
40,320
120
540 k
4
4
8
840
2,520
1272
352
October 2008
© 2008 Actel Corporation
i
See the Actel website for the latest version of the datasheet.
All RTAX4000S information is preliminary.
RTAX-S/SL RadTolerant FPGAs
Ordering Information
RTAX2000S/SL _
1
CGS
624
B
Application
B = MIL-STD 883
Class
B
E = E-Flow (Actel
Space-Level
Flow)
EV =
Class
V Equivalent Flow Processing
Consistent
with MIL-PRF 38535
Package Lead
Count
Package Type
CQ
=
Ceramic
Quad Flat Pack
CG
=
Ceramic Column Grid
Array
LG = Land
Grid
Array
S
=
Six Sigma Column
B = BAE
Column
Speed Grade
Blank =
Standard Speed
1 = Approximately 15% Faster than
Standard
Part Number
S
=
Standard
Family
SL
= Low-Power Option
RTAX250S/SL = 250,000 Equivalent
System Gates
RTAX1000S/SL = 1,000,000 Equivalent
System Gates
RTAX2000S/SL = 2,000,000 Equivalent
System Gates
RTAX4000S = 4,000,000 Equivalent
System Gates
Note:
PROTO refers to the RTAX-S/SL Prototype Units. All
CCGA
PROTO units will
be
offered with the
Six Sigma Column.
Temperature Grade Offerings
Package
CQ208
CQ256
CQ352
CG624*/LG624
CG1152/LG1152
CG1272/LG1272
RTAX250S/SL
B, E, EV
–
B, E, EV
–
–
–
RTAX1000S/SL
–
–
B, E, EV
B, E, EV
–
–
RTAX2000S/SL
–
B, E, EV
B, E, EV
B, E, EV
B, E, EV
–
RTAX4000S
–
–
B, E, EV
–
–
B, E, EV
Note:
*Indicates that the CG624 package will be offered as CGS624 for the Six Sigma column and CGB624 for the BAE column. The
other CCGA offerings (1152 and 1272) will be offered as Six Sigma columns.
B = MIL-STD-883 Class B
E = E-Flow (Actel Space-Level Flow)
EV = Actel "V" Equivalent Flow (Class V processing consistent with MIL-PRF 38535)
ii
v5.3
RTAX-S/SL RadTolerant FPGAs
Speed Grade and Temperature Grade Matrix
Std
B
E
EV
✓
✓
✓
–1
✓
✓
✓
Contact your local Actel representative for device availability.
Device Resources
Device
CQ208
CQ256
CQ352
CG624/LG624
CG1152/LG1152
CG1272/LG1272
User I/Os (Including Clock Buffers)
RTAX250S/SL
RTAX1000S/SL
RTAX2000S/SL
115
–
–
–
–
138
198
198
198
–
418
418
–
–
684
–
–
–
RTAX4000S
–
–
166
–
–
840
Note:
CQFP = Ceramic Quad Flat Pack and CCGA = Ceramic Column Grid Array, LGA = Land Grid Array
v5.3
iii
RTAX-S/SL RadTolerant FPGAs
Actel MIL-STD-883 Class B Product Flow
Table 2 •
Actel MIL-STD-883 Class B Product Flow for RTAX-S/SL
1, 2
Step
1
2
3
4
Internal Visual
Serialization
Temperature Cycling
Constant Acceleration
1010, Condition C, 10 cycles minimum
2001, Y1 Orientation Only
Condition B for CQ352, LG624, LG1152
Condition D for CQ208
TBD for LG1272
2020, Condition A
1014
In accordance
specification
with
applicable
Actel
device
Screen
2010, Condition B
Method
Requirement
100%
100%
100%
100%
5
6
7
8
9
10
11
Particle Impact Noise Detection
Seal (Fine & Gross Leak Test)
Pre-Burn-In Electrical Parameters
Dynamic Burn-In
Interim (Post-Burn-In) Electrical Parameters
Percent Defective Allowable (PDA) Calculation
Final Electrical Test
2
a. Static Tests
(1) 25°C
(2) –55°C and +125°C
b. Functional Tests
(1) 25°C
(2) –55°C and +125°C
c. Switching Tests at 25°C
100%
100%
100%
100%
100%
All Lots
device
100%
1015, Condition D,
160 hours at 125°C or 80 hours at 150°C minimum
In accordance
specification
5%
In accordance with applicable Actel
specification, which includes a, b, and c:
5005, Table 1, Subgroup 1
5005, Table 1, Subgroup 2, 3
with
applicable
Actel
device
5005, Table 1, Subgroup 7
5005, Table 1, Subgroup 8a, 8b
5005, Table 1, Subgroup 9
2009
100%
12
Notes:
External Visual
1. For CCGA devices, all Assembly, Screening, and TCI testing are performed at LGA level. Only QA electrical and mechanical visual are
performed after solder column attachment.
2. RTAX-S and RTAX-SL devices have the same silicon and are distinguished by screening the I
CCA
current limits at 125°C final electrical
test.
iv
v5.3
RTAX-S/SL RadTolerant FPGAs
Actel Extended Flow
Table 3 •
Actel Extended Flow for RTAX-S/SL
1, 2, 3, 4
Step
1
2
3
4
5
Internal Visual
Serialization
Temperature Cycling
Constant Acceleration
1010, Condition C, 10 cycles minimum
2001, Y1 Orientation Only
Condition B for CQ352, LG624, LG1152
Condition D for CQ208
TBD for LG1272
2020, Condition A
2012, One View (Y1 Orientation) Only
In accordance
specification
with
applicable
Actel
device
100%
100%
100%
Screen
Destructive Bond Pull
5
2011, Condition D
2010, Condition A
Method
Requirement
Extended Sample
100%
100%
100%
6
7
8
9
Particle Impact Noise Detection
Radiographic (X-Ray)
Pre-Burn-In Electrical Parameters
Dynamic Burn-In
1015, Condition D,
240 hours at 125°C or 120 hours at 150°C
minimum
Electrical In accordance
specification
with
applicable
Actel
device
10
11
12
13
14
Interim
(Post-Dynamic-Burn-In)
Parameters
Static Burn-In
100%
100%
100%
All Lots
100%
1015, Condition C, 72 hours at 150°C or 144
hours at 125°C minimum
In accordance
specification
with
applicable
Actel
device
Interim (Post-Static-Burn-In) Electrical Parameters
Percent Defective Allowable (PDA) Calculation
Final Electrical Test
4
a. Static Tests
(1) 25°C
(2) –55°C and +125°C
b. Functional Tests
(1) 25°C
(2) –55°C and +125°C
c. Switching Tests at 25°C
5% Overall, 3% Functional Parameters at 25°C
In accordance with applicable Actel
specification, which includes a, b, and c:
5005, Table 1, Subgroup 1
5005, Table 1, Subgroup 2, 3
device
5005, Table 1, Subgroup 7
5005, Table 1, Subgroup 8a, 8b
5005, Table 1, Subgroup 9
1014
2009
100%
100%
15
16
Notes:
Seal (Fine & Gross Leak Test)
External Visual
1. Actel offers Extended Flow for users requiring additional screening beyond MIL-STD-833, Class B requirement. Actel is offering this
Extended Flow incorporating the majority of the screening procedures as outlined in Method 5004 of MIL-STD-883, Class S.
2. The Quality Conformance Inspection (QCI) for Extended Flow devices still comply to MIL-STD-833, Class B requirement.
3. For CCGA devices, all Assembly/Screening/TCI testing are performed at LGA level. Only QA electrical and mechanical visual are
performed after solder column attachment.
4. RTAX-S and RTAX-SL devices have the same silicon and are distinguished by screening the I
CCA
current limits at 125°C final electrical
test.
5. Requirement for 100% nondestructive bond pull per Method 2003 is substituted by an extensive destructive bond pull to Method
2011 Condition D on an extended sample basis.
v5.3
v
