Rev.3.1_
00
BATTERY PROTECTION IC (FOR A 3-SERIAL-CELL PACK)
S-8233B SERIES
The 8233B is a series of lithium-ion rechargeable battery protection ICs
incorporating high-accuracy (±25 mV) voltage detection circuits and
delay circuits. It is suitable for a 3-serial-cell lithium-ion battery pack.
Features
(1)
Internal high-accuracy voltage detection circuit
Over charge detection voltage
Over charge release voltage
3.80
±
0.025 V to 4.40
±
0.025 V
5 mV - step
3.45
±
0.100 V to 4.40
±
0.100 V
5 mV - step
(The over charge release voltage can be selected within the range where a difference from over
charge detection voltage is 0 to 0.35 V with 50 mV - step)
Over discharge detection voltage
Over discharge release voltage
2.00
±
0.08 V to 2.80± 0.08 V
50 mV - step
2.00
±
0.10 V to4.00± 0.10 V
50.mV - step
(The over discharge release voltage can be selected within the range where a difference from
over discharge detection voltage is 0 to 1.2V with 50 mV - step)
Over current detection voltage 1
0.15 V
±10%
to 0.50 V
±10%
50 mV - step
(2)
(3)
(4)
(5)
(6)
(7)
(8)
High input-voltage device (absolute maximum rating: 26 V)
Wide operating voltage range:
2 V to 24 V
The delay time for every detection can be set via an external capacitor.
Three over current detection levels (protection for short-circuiting)
Internal charge/discharge prohibition circuit via the control terminal
The function for charging batteries from 0 V is available.
Low current consumption
Operation
Power-down
(9)
50µA max. (+25°C)
0.1µA max. (+25°C)
16-pin TSSOP package
Applications
Lithium-ion rechargeable battery packs
Seiko Instruments Inc.
1
Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
Rev.3.1_
00
Selection Guide
Table1
Model/Item
Over charge
detection
voltage
S-8233BAFT 4.225±0.025V
S-8233BBFT 4.325±0.025V
Over charge Over discharge Over discharge
release
voltage
*1
4.10±0.10V
detection
voltage
2.30±0.08V
2.30±0.08V
2.70±0.10V
2.70±0.10V
release voltage
Over current
detection
voltage1
0.20V±10%
0.20V±10%
0V battery
charging
function
-
-
Available
Unavailable
normal
reverse
Conditioning
function
CTL logic
*1) Without over charge detection / release hysteresis.
*2) The input voltage of CTL for normal condition is changed by the CTL logic. (Please refer description).
Change in the detection voltage is available in products other than the above listed ones. Contact the
SII Semiconductor Products Sales Department.
2
Seiko Instruments Inc.
Rev.3.1_
00
Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
Block Diagram
VCC
Reference
voltage 1
Over current
2,3 delay circuit
Over current
detection
circuit
VMP
+
−
CD1
Battery 1
Over charge
+
−
Battery 1
Over discharge
Over current‚P
delay circuit
COVT
VC1
Battery 1
Over charge
+
−
Battery 2
Over charge
Over discharge
delay circuit
CDT
Control
Logic
Over charge
delay circuit
CD2
+
−
Battery 2
Over discharge
CCT
Reference
voltage 2
VC2
Battery 2
Over charge
+
−
Battery 3
Over charge
DOP
CD3
+
Battery 3
Over discharge
Reference
voltage 3
−
COP
VSS
Battery 3
Over charge
Floating
detection circuit
CTL
Figure 1
The delay time for over current detection 2 and 3 is fixed by an internal IC circuit. The delay time
cannot be changed via an external capacitor.
Seiko Instruments Inc.
3
Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
Rev.3.1_
00
Pin Assignment
Top View
DOP
NC
COP
VMP
COVT
CDT
CCT
VSS
1
2
3
4
16
15
14
13
12
11
10
9
VCC
NC
CD1
VC1
CD2
VC2
CD3
CTL
Pin Description
Table 2
No.
1
3
4
5
6
7
8
9
10
11
12
13
14
16
2,15
Name
DOP
COP
VMP
Description
Connects FET gate for discharge control (CMOS output)
Connects FET gate for charge control (Nch open-drain output)
Detects voltage between VCC to VMP(Over current detection pin)
COVT Connects capacitor for over current detection1delay circuit
CDT
CCT
VSS
CTL
CD3
VC2
CD2
VC1
CD1
VCC
NC
Connects capacitor for over discharge detection delay circuit
Connects capacitor for over charge detection delay circuit
Negative power input, and connects negative voltage for battery 3
Charge/discharge control signal input
Battery 3 conditioning signal output
Connects battery 2 negative voltage and battery 3 positive voltage
Battery 2 conditioning signal output
Connects battery 1 negative voltage and battery 2 positive voltage
Battery 1 conditioning signal output
Positive power input and connects battery 1 positive voltage
Non connect
5
6
7
8
T S S O P -16
Figure 2
Absolute Maximum Ratings
Table 3
Item
Input voltage between VCC and VSS
Input terminal voltage
VMP Input terminal voltage
CD1 output terminal voltage
CD2 output terminal voltage
CD3 output terminal voltage
DOP output terminal voltage
COP output terminal voltage
Power dissipation
Operating temperature range
Storage temperature range
Sym.
VDS
VIN
VVMP
VCD1
VCD2
VCD3
VDOP
VCOP
PD
Topr
Tstg
VC1,VC2,CTL,CCT,CDT,COVT
VMP
CD1
CD2
CD3
DOP
COP
TSSOP-16PKG
Applied Pins
Rating
VSS-0.3 to VSS+26
VSS-0.3 to VCC+0.3
VSS-0.3 to VSS+26
VC1-0.3 to VCC+0.3
VC2-0.3 to VCC+0.3
VSS-0.3 to VCC+0.3
VSS-0.3 to VCC+0.3
VSS-0.3 toVVMP+0.3
300
-20 to +70
-40 to +125
Ta = 25°C
Unit
V
V
V
V
V
V
V
V
mW
°C
°C
4
Seiko Instruments Inc.
Rev.3.1_
00
Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
Electrical Characteristics
Table 4
Item
Detection voltage
Over charge detection
voltage1
Over charge release
voltage1
Over discharge detection
voltage1
Over discharge release
voltage1
Over charge detection
voltage 2
Over charge release
voltage 2
Over discharge detection
voltage 2
Over discharge release
voltage 2
Over charge detection
voltage 3
Over charge release
voltage 3
Over discharge detection
voltage 3
Over discharge release
voltage 3
Over current detection
voltage1
Over current detection
voltage 2
Over current detection
voltage 3
Voltage temperature
factor 1
Voltage temperature
factor 2
Delay time
Over charge detection
delay time1
Over charge detection
delay time 2
Over charge detection
delay time 3
Over discharge detection
delay time1
Over discharge detection
delay time 2
Over discharge detection
delay time 3
Over current detection
delay time1
Over current detection
delay time 2
Over current detection
delay time 3
Operating voltage
Operating voltage
between VCC and VSS
Symbol
condition Test
circuit
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
Notice
Min.
Typ.
Max.
Ta = 25°C
Unit
VCU1
VCD1
VDD1
VDU1
VCU 2
VCD 2
VDD 2
VDU 2
VCU 3
VCD 3
VDD 3
VDU 3
VIOV1
VIOV2
VIOV3
TCOE1
TCOE2
3.80 to 4.40 Adjustment VCU1-0.025
3.45 to 4.40 Adjustment
2.00 to 2.80 Adjustment
2.00 to 4.00 Adjustment
VCD1-0.10
VDD1-0.08
VDU1-0.10
VCU1
VCD1
VDD1
VDU1
VCU2
VCD2
VDD2
VDU2
VCU3
VCD3
VDD3
VDU3
VIOV1
0.6
2.0
0
0
VCU1+0.025
VCD1+0.10
VDD1+0.08
VDU1+0.10
VCU2+0.025
VCD2+0.10
VDD2+0.08
VDU2+0.10
VCU3+0.025
VCD3+0.10
VDD3+0.08
VDU3+0.10
VIOV1×1.1
0.66
3.0
1.0
0.5
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mV/°C
mV/°C
3.80 to 4.40 Adjustment VCU2-0.025
3.45 to 4.40 Adjustment
2.00 to 2.80 Adjustment
2.00 to 4.00 Adjustment
VCD2-0.10
VDD2-0.08
VDU2-0.10
3.80 to 4.40 Adjustment VCU3-0.025
3.45 to 4.40 Adjustment
2.00 to 2.80 Adjustment
2.00 to 4.00 Adjustment
(*4)0.15 to 0.50V
Adjustment
VCC Reference
VSS Reference
(*1)Ta=-20 to 70°C
(*2)Ta=-20 to 70°C
VCD3-0.10
VDD3-0.08
VDU3-0.10
VIOV1×0.9
0.54
1.0
-1.0
-0.5
tCU1
tCU2
tCU3
tDD1
tDD2
tDD3
tIOV1
tIOV2
tIOV3
9
10
11
9
10
11
12
12
12
6
6
6
6
6
6
7
7
7
CCCT=0.47µF
CCCT=0.47µF
CCCT=0.47µF
CCDT=0.1µF
CCDT=0.1µF
CCDT=0.1µF
CCOVT=0.1µF
0.5
0.5
0.5
20
20
20
10
2
1.0
1.0
1.0
40
40
40
20
4
300
1.5
1.5
1.5
60
60
60
30
8
550
S
S
S
mS
mS
mS
mS
mS
µ
S
FET gate capacitor
=2000pF
(*3)
100
VDSOP
2.0
-
24
V
Seiko Instruments Inc.
5
