®
DEVICE
SPECIFICATION
SERIAL BACKPLANE RETIMER DEVICE
BiCMOS PECL CLOCK GENERATOR
SERIAL BACKPLANE RETIMER DEVICE
GENERAL DESCRIPTION
S2092
S2092
FEATURES
•
•
•
On-chip high frequency PLL with internal
loop filter for clock recovery
Internal 100
Ω
line-to-line termination on
high speed differential input
Supports data recovery from:
2.488 to 2.67 Gbps (2.488 Gbps with FEC
overhead data rate capability)
Selectable reference frequencies
Lock detect—monitors frequency of
incoming data
Low-jitter serial CML interface
Single +3.3 V supply, 455 mW power
dissipation (typ)
Compact 7 mm x 7 mm 48 pin TQFP/TEP
package
The function of the S2092 retimer device is to derive
high speed timing signals for DWDM equipment. The
S2092 is implemented using AMCC’s proven Phase
Lock Loop (PLL) technology. Figure 1 shows a typical
network application.
The S2092 can receive a 2.488 Gbps to 2.67 Gbps
scrambled NRZ signal. This range is dependent on
the user's FEC needs and reference frequency selec-
tion. The S2092 recovers the clock from the data
and outputs the retimed data.
The S2092 utilizes an on-chip PLL which consists
of a phase detector, a loop filter, and a Voltage
Controlled Oscillator (VCO). The phase detector
compares the phase relationship between the VCO
output and the serial data input. A loop filter con-
verts the phase detector output into a smooth DC
voltage, and the DC voltage is input to the VCO
whose frequency is varied by this voltage. A block
diagram is shown in Figure 2.
•
•
•
•
•
APPLICATIONS
•
•
•
•
Dense Wavelength Division Multiplexing
(DWDM) systems
Serial Backplane interfaces
2.488 Gbps to 2.67 Gbps Short Haul
Retiming
Crosspoint interfaces
Figure 1. System Block Diagram
Port Card
S3056
S3057
S3052
S3056
S3056
S3057
S3052
S3057
S2092
S2092
S3057
Port Card
S3057
S3052
Switch Card
S2092
S2092
S3056
S3057
S3052
S2018
S2092
S3056
S3057
S3052
S3056
S3056
S3057
S3052
S3057
S3057
S3052
S3057
S2092
S2092
S2092
S3056
S3057
S3052
Port Card
Port Card
July 10, 2000 / Revision A
1
S2092
S2092 OVERVIEW
The S2092 supports clock recovery from 2.488 Gbps
to 2.67 Gbps data rate. Differential serial data is input
to the chip at the specified rate, and clock recovery is
performed on the incoming data stream. An external
oscillator is required to minimize the PLL lock time.
Retimed data is output from the S2092.
SERIAL BACKPLANE RETIMER DEVICE
Suggested Interface Devices
AMCC
AMCC
AMCC
AMCC
AMCC
AMCC
AMCC
AMCC
S2018
S3083
S3063
S3044
S3057
S3067
S3056
S3052
17 x 17 3.2 Gbps Crosspoint Switch
OC-48 16:1Transmitter
OC-48 Differential 16:1 Transmitter
OC-48 1:16 Receiver
Multi-Rate SONET/SDH/ATM
Transceiver
Multi-Rate SONET/SDH/ATM
Transceiver w/FEC
Mulit-Rate Clock and Data
Recovery Unit
Mulit-Rate Performance Monitor
Figure 2. S2092 Functional Block Diagram
CAP 1,2
2
LOOP
FILTER
VCO
TESTOUT 1
TESTOUT 2
REFCLKP/N
TESTCLK
REFSEL
TESTEN
LCKREFN
LOCK
DETECTOR
CLOCK
DIVIDER
LOCKDET
RST
PHASE DETECTOR
SERDATOP/N
SDN
SERDATIP/N
BYPASS
2
July 10, 2000 / Revision A
SERIAL BACKPLANE RETIMER DEVICE
S2092 FUNCTIONAL DESCRIPTION
The S2092 retimer device performs clock recovery
function from 2.488 Gbps to 2.67 Gbps serial data
links. The chip extracts the clock from the serial data
inputs and provides retimed data outputs. A 155.52
to 166.63 or 19.44 to 20.83 MHz reference clock is
required (REFCLK frequency is dependent on which
FEC capability is required. See Table 2 for the
number of bytes per 255 byte block to set the proper
reference frequency.) for phase lock loop start up
and proper operation under loss of signal conditions.
An integral prescaler and phase lock loop circuit is
used to multiply this reference to the nominal bit rate.
Data Retiming
Data retiming, as shown in the block diagram in Fig-
ure 2, generates a clock that is at the same fre-
quency as the incoming data bit rate at the serial
data input. The clock is phase aligned by a PLL so
that it samples the data in the center of the data eye
pattern.
The phase relationship between the edge transi-
tions of the data and those of the generated clock
are compared by a phase/frequency discriminator.
Output pulses from the discriminator indicate the
required direction of phase corrections. These
pulses are smoothed by an integral loop filter. The
output of the loop filter controls the frequency of
the Voltage Controlled Oscillator (VCO), which
generates the recovered clock.
S2092
Frequency stability without incoming data is guaran-
teed by an alternate reference input (REFCLK) that
the PLL locks onto when data is lost. If the frequency
of the incoming signal varies by a value greater than
that stated in Table 7 with respect to REFCLKP/N,
the PLL will be declared out of lock, and the PLL will
lock to the reference clock. The assertion of SDN will
also cause an out of lock condition.
The loop filter transfer function is optimized to enable
the PLL to track the jitter, yet tolerate the minimum
transition density in a received data signal.
Lock Detect
The S2092 contains a lock detect circuit which monitors
the integrity of the serial data inputs. If the received
serial data fails the frequency test, the PLL will be
forced to lock to the local reference clock. This will
maintain the correct frequency of the recovered clock
output under loss of signal or loss of lock conditions. If
the recovered clock frequency deviates from the local
reference clock frequency by more than that stated in
Table 7, the PLL will be declared out of lock. The lock
detect circuit will poll the input data stream in an attempt
to reacquire lock to data. If the recovered clock fre-
quency is determined to be within that range stated in
Table 7, the PLL will be declared in lock and the lock
detect output will go active. The assertion of SDN will
also cause an out of lock condition.
Table 1. Reference Frequency Select
REFSEL
0
1
Reference Frequency
19.44 to 20.83 MHz
155.52 to 166.63 MHz
Table 2. FEC Modes
Reference Frequency for Data Rates with FEC Capability of X bytes per 255–Byte Block
REFSEL
X=0
0
1
19.44 MHz
155.52 MHz
X=3
19.99 MHz
X=4
20.15 MHz
X=5
20.31 MHz
X=6
20.48 MHz
X=7
20.65 MHz
X=8
20.83 MHz
159.91MHz 161.21 MHz 162.53 MHz 163.87 MHz 165.26 MHz 166.63 MHz
July 10, 2000 / Revision A
3
S2092
CHARACTERISTICS
Input Jitter Tolerance
Input jitter tolerance is defined as the peak to
peak amplitude of sinusoidal jitter applied on the
input signal that causes an equivalent 1 dB opti-
cal/electrical power penalty. See Figure 3.
Jitter Transfer
The jitter transfer function is defined as the ratio of
jitter on the output signal to the jitter applied on the
input signal versus frequency. Jitter transfer require-
ments are shown in Figure 4. The measurement con-
dition is that input sinusoidal jitter up to the mask
level in Figure 4 be applied.
Jitter Generation
The jitter of the serial data outputs shall not exceed
the value specified in Table 7. The conditions are
stated with a serial data input with no jitter presented
on SERDATIP/N. (See Table 7).
SERIAL BACKPLANE RETIMER DEVICE
Figure 3. Input Jitter Tolerance Specification
Sinusodal
Input Jitter
Amplitude
(UI p-p)
15
1.5
0.15
f0
f1
f2
f3
ft
Data Rate
2.488 Gbps
f0
(Hz)
10
f1
(Hz)
600
f2
(Hz)
6000
f3
(kHz)
100
ft
(kHz)
1000
Figure 4. Jitter Transfer Specification
P
slope = -20 dB/decade
Jitter
Transfer
Acceptable
Range
fc
Frequency
Data Rate
2.488 Gbps
fc
(kHz)
2000
P
(dB)
0.1
4
July 10, 2000 / Revision A
SERIAL BACKPLANE RETIMER DEVICE
Table 3. Pin Assignment and Descriptions
Pin Name
SERDATIP
SERDATIN
BYPASS
Level
Diff.
CML
LVTTL
I/O
Pin#
3
2
46
Description
S2092
I
Serial Data In. Clock is recovered from the transitions on these inputs.
Internally biased and terminated. (See Figure 8.)
Active High. Used to bypass the PLL. It allows transmission of the data
input without clock recovery.
Signal Detect. Active Low. A single-ended 10K PECL input to be driven
by the external optical receiver module to indicate a loss of received
optical power. When SDN is inactive, the data on the Serial Data In
(SERDATIP/N) pins will be internally forced to a constant zero and the
PLL will be forced to lock to the REFCLK input. When SDN is active,
data on the SERDATIP/N pins will be processed normally.
Reference Clock. 155.52 to 166.63 or 19.44 to 20.83 MHz (see Tables
1 and 2 for additional reference clock frequencies) input used to
establish the initial operating frequency of the clock recovery PLL and
also used as a standby clock in the absence of data, during reset, or
when SDN is inactive. Internally biased.
Loop Filter Capacitor. The external loop filter capacitor and resistors
are connected to these pins. (See Figure 11.)
Lock to Reference. Active Low. When active, the serial data output will
be invalid.
Test input signal used for production test. Leave open (no DC
connection) for normal operation.
Selects the reference frequency (See Tables 1 and 2.)
Active High. Resets lock detect circuit and VCO divide-by-N circuit for
production test.
Test Enable. Active High. Bypasses the VCO for production test. Tie
Low for normal operation.
Serial Data Out. This signal is the delayed version of the incoming data
stream (SERDATI).
Lock Detect. Clock recovery indicator. Set High when the internal clock
recovery has locked onto the incoming data stream. LOCKDET is an
asynchronous output.
Test Output. Leave open (no DC connection) for normal operation.
Test Output. Leave open (no DC connection) for normal operation.
Test Mode Control. Keep High for normal operation.
Test Mode Control. Keep High for normal operation.
I
SDN
Single
Ended
LVPECL
I
45
REFCLKP
REFCLKN
Internally
Biased
Diff.
LVPECL
I
6
7
CAP1
CAP2
LCKREFN
TESTCLK
REFSEL
RST
TESTEN
SERDATOP
SERDATON
LOCKDET
TESTOUT1
TESTOUT2
TESTMODE1
TESTMODE2
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Diff.
CML
LVTTL
I
40
39
17
15
18
16
47
28
27
10
23
33
19
20
I
I
I
I
I
O
O
O
O
I
I
July 10, 2000 / Revision A
5
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