S25FL Family (Serial Peripheral Interface)
S25FL016M
16 Megabit CMOS 3.0 Volt Flash Memory
with 50 Mhz SPI Bus Interface
ADVANCE
INFORMATION
Distinctive Characteristics
ARCHITECTURAL ADVANTAGES
Single power supply operation
— Full voltage range: 2.7 to 3.6 V read and program
operations
Memory Architecture
— Thirty-two sectors with 512 Kb each
Program
— Page Program (up to 256 bytes) in 1.5 ms (typical)
— Program cycles are on a page by page basis
Erase
— 1.5 s typical sector erase time
— 48 s typical bulk erase time
Cycling Endurance
— 100,000 cycles per sector typical
Data Retention
— 20 years typical
Device ID
— JEDEC standard two-byte electronic signature
— RES instruction one-byte electronic signature for
backward compatibility
Process Technology
— Manufactured on 0.20 µm MirrorBit
TM
process
technology
Package Option
— Industry Standard Pinouts
— 16-pin SO package (300 mils)
— 8-Contact WSON Package (8x6mm), No-Lead
PERFORMANCE CHARACTERISTICS
Speed
— 50 MHz clock rate (maximum)
Power Saving Standby Mode
— Standby Mode 50 µA (max)
— Deep Power Down Mode 1 µA (typical)
Memory Protection Features
Memory Protection
— W# pin works in conjunction with Status Register Bits
to protect specified memory areas
— Status Register Block Protection bits (BP2, BP1, BP0)
in status register configure parts of memory as read-
only
SOFTWARE FEATURES
SPI Bus Compatible Serial Interface
Publication Number
S25FL016M
Revision
A
Amendment
0
Issue Date
July 13, 2004
A d v a n c e
I n f o r m a t i o n
General Description
The S25FL016M device is a 3.0 Volt (2.7 V to 3.6 V) single power supply Flash memory
device. S25FL016M consists of thirty-two sectors, each with 512 Kb memory.
Data appears on SI input pin when inputting data into the memory and on the SO output
pin when outputting data from the memory. The devices are designed to be programmed
in-system with the standard system 3.0 Volt V
CC
supply.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program in-
struction.
The memory supports Sector Erase and Bulk Erase instructions.
Each device requires only a 3.0 Volt power supply (2.7 V to 3.6 V) for both read and write
functions. Internally generated and regulated voltages are provided for the program op-
erations. This device does not require V
PP
supply.
2
S25FL Family (Serial Peripheral Interface) S25FL016M
S25FL016M_00_A0_E July 13, 2004
P r e l i m i n a r y
Table of Contents
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . .2
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . .5
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .7
Table 1. S25FL Valid Combinations Table . . . . . . . . . . . . . . . .7
Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 12. Page Program (PP) Instruction Sequence . . . . . . . 23
Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 13. Sector Erase (SE) Instruction Sequence . . . . . . . . 24
Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 14. Bulk Erase (BE) Instruction Sequence. . . . . . . . . . 25
Deep Power Down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 15. Deep Power Down (DP) Instruction Sequence . . . . 26
Release from Deep Power Down (RES) . . . . . . . . . . . . . . . . . .26
Figure 16. Release from Deep Power Down Instruction Sequence
27
Signal Description .....................................................................................8
SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 1. Bus Master and Memory Devices on the SPI Bus . . . . 9
Figure 2. SPI Modes Supported. . . . . . . . . . . . . . . . . . . . . . . 9
Release from Deep Power Down and Read Electronic
Signature (RES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Figure 17. Release from Deep Power Down and Read
Electronic Signature (RES) Instruction Sequence. . . . . . . . . . 28
Operating Features . . . . . . . . . . . . . . . . . . . . . . . . 10
Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2. Protected Area Sizes (S25FL016M). . . . . . . . . . . . . .11
Power-up and Power-down . . . . . . . . . . . . . . . . . . 28
Figure 18. Power-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 19. Power-Down and Voltage Drop. . . . . . . . . . . . . . . 29
Table 6. Power-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . 30
Hold Condition Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 3. Hold Condition Activation . . . . . . . . . . . . . . . . . . . 12
Memory Organization . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Sector Address Table – S25FL016M . . . . . . . . . . . . .13
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 4. Write Enable (WREN) Instruction Sequence............. 15
Write Disable (WRDI)...........................................................................16
Figure 5. Write Disable (WRDI) Instruction Sequence ............ 16
Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . 30
Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 30
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .31
CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 7. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 31
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 6. Read Status Register (RDSR) Instruction Sequence . 17
Figure 7. Status Register Format . . . . . . . . . . . . . . . . . . . . 17
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 20. AC Measurements I/O Waveform.........................
Table 8. Test Specifications . . . . . . . . . . . . . . . . . . . . . . . .
Table 9. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .
Figure 21. SPI Mode 0 (0,0) Input Timing. . . . . . . . . . . . . . .
Figure 22. SPI Mode 0 (0,0) Output Timing. . . . . . . . . . . . . .
Figure 23. HOLD# Timing . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 24. Write Protect Setup and Hold Timing during
WRSR when SRWD=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
32
33
34
34
35
35
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8. Write Status Register (WRSR) Instruction Sequence 19
Table 5. Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . .19
Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. Read Data Bytes (READ) Instruction Sequence . . . . 20
Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . 20
Figure 10. Read Data Bytes at Higher Speed (FAST_READ)
Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 11. Read Identification (RDID) Instruction Sequence and
Data-Out Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 36
S016 wide—16-pin Plastic Small Outline 300mils Body
Width Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
WSON 8-contact (8x6mm) No-Lead Package . . . . . . . . . . . . 37
Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
July 13, 2004 S25FL016M_A0_E
S25FL Family (Serial Peripheral Interface) S25FL016M
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A d v a n c e
I n f o r m a t i o n
Block Diagram
SRAM
PS
Array - L
Logic
X
D
E
C
Array - R
RD
DATA PATH
IO
CS#
4
S25FL Family (Serial Peripheral Interface) S25FL016M
HOLD#
SCK
GND
SI
VCC
SO
S25FL016M_00_A0_E July 13, 2004
A d v a n c e
I n f o r m a t i o n
Connection Diagrams
16-pin Plastic Small Outline Package (SO)
HOLD#
VCC
NC
NC
NC
NC
CS#
SO
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SCK
SI
NC
NC
NC
NC
GND
W#
Input/Output Descriptions
SCK
SI
SO
CS#
W#
HOLD#
V
CC
GND
=
=
=
=
=
=
=
=
Serial Clock Input
Serial Data Input
Serial Data Output
Chip Select Input
Write Protect Input
Hold Input
Supply Voltage Input
Ground Input
July 13, 2004 S25FL016M_00_A0_E
S25FL Family (Serial Peripheral Interface) S25FL016M
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