S25FL032P
32-Mbit 3.0 V Flash Memory
This product family has been retired and is not recommended for designs. For new and current designs, S25FL064L supersede
S25FL032P. These are the factory-recommended migration paths. Refer to the S25FL-L Family datasheets for specifications and
ordering information.
Distinctive Characteristics
Architectural Advantages
Single power supply operation
– Full voltage range: 2.7 V to 3.6 V read and write operations
Memory architecture
– Uniform 64-KB sectors
– Top or bottom parameter block (two 64-KB sectors (top
or bottom) broken down into 16 4-KB sub-sectors each)
– 256-byte page size
– Backward compatible with the S25FL032A device
Program
– Page Program (up to 256 bytes) in 1.5 ms (typical)
– Program operations are on a page by page basis
– Accelerated programming mode via 9-V W#/ACC pin
– Quad Page Programming
Erase
– Bulk erase function
– Sector erase (SE) command (D8h) for 64-KB sectors
– Sub-sector erase (P4E) command (20h) for 4-KB sectors
– Sub-sector erase (P8E) command (40h) for 8-KB sectors
Cycling endurance
– 100,000 cycles per sector typical
Data retention
– 20 years typical
Device ID
– JEDEC standard two-byte electronic signature
– RES command one-byte electronic signature for backward
compatibility
One time programmable (OTP) area for permanent, secure
identification; can be programmed and locked at the factory
or by the customer
Common Flash Interface (CFI) compliant: allows host system
to identify and accommodate multiple flash devices
Process technology
– Manufactured on 0.09
m MirrorBit
®
process technology
Package option
– Industry Standard Pinouts
– 8-pin SO package (208 mils)
– 16-pin SO package (300 mils)
– 8-contact USON package (5
6 mm)
– 8-contact WSON package (6
8 mm)
– 24-ball BGA 6
8 mm package, 5
5 pin configuration
– 24-ball BGA 6
8 mm package, 6
4 pin configuration
Performance Characteristics
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Speed
– Normal READ (Serial): 40-MHz clock rate
– FAST_READ (Serial): 104-MHz clock rate (maximum)
– DUAL I/O FAST_READ: 80-MHz clock rate or
20 MB/s effective data rate
– QUAD I/O FAST_READ: 80 MHz clock rate or
40 MB/s effective data rate
Power saving standby mode
– Standby Mode 80
A (typical)
– Deep Power-Down Mode 3
A (typical)
Memory Protection Features
Memory protection
– W#/ACC pin works in conjunction with Status Register Bits
to protect specified memory areas
– Status Register Block Protection bits (BP2, BP1, BP0) in
status register configure parts of memory as read-only
Cypress Semiconductor Corporation
Document Number: 002-00650 Rev. *L
•
198 Champion Court
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San Jose
,
CA 95134-1709
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408-943-2600
Revised May 19, 2017
S25FL032P
General Description
The S25FL032P is a 3.0 V (2.7 V to 3.6 V), single-power-supply Flash memory device. The device consists of 64 uniform 64-KB
sectors with the two (top or bottom) 64-KB sectors further split up into thirty-two 4-KB sub sectors. The S25FL032P device is fully
backward compatible with the S25FL032A device.
The device accepts data written to Serial Input (SI) and outputs data on Serial Output (SO). The devices are designed to be
programmed in-system with the standard system 3.0-V V
CC
supply.
The S25FL032P device adds the following high-performance features using five new instructions:
Dual Output Read using both SI and SO pins as output pins at a clock rate of up to 80 MHz
Quad Output Read using SI, SO, W#/ACC, and HOLD# pins as output pins at a clock rate of up to 80 MHz
Dual I/O High Performance Read using both SI and SO pins as input and output pins at a clock rate of up to 80 MHz
Quad I/O High Performance Read using SI, SO, W#/ACC, and HOLD# pins as input and output pins at a clock rate of up to
80 MHz
Quad Page Programming using SI, SO, W#/ACC, and HOLD# pins as input pins to program data at a clock rate of up to 80 MHz
The memory can be programmed 1 to 256 bytes at a time, using the Page Program command. The device supports Sector Erase
and Bulk Erase commands.
Each device requires only a 3.0-V power supply (2.7 V to 3.6 V) for both read and write functions. Internally generated and regulated
voltages are provided for the program operations. This device requires a high voltage supply to the W#/ACC pin to enable the
Accelerated Programming mode.
The S25FL032P device also offers a One-Time Programmable area (OTP) of up to 128 bits (16 bytes) for permanent secure
identification and an additional 490 bytes of OTP space for other use. This OTP area can be programmed or read using the OTPP or
OTPR instructions.
Document Number: 002-00650 Rev. *L
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S25FL032P
Contents
1.
2.
3.
4.
5.
5.1
6.
7.
7.1
7.2
7.3
7.4
7.5
Block Diagram..............................................................
4
Connection Diagrams..................................................
5
Input/Output Descriptions...........................................
7
Logic Symbol
............................................................... 7
Ordering Information
................................................... 8
Valid Combinations ........................................................ 9
SPI Modes...................................................................
10
11
11
11
11
11
11
11
12
12
13
14
15
9.19
9.20
9.21
9.22
9.23
10.
10.1
10.2
10.3
11.
12.
13.
Deep Power-Down (DP) ............................................... 38
Release from Deep Power-Down (RES)....................... 39
Clear Status Register (CLSR)....................................... 40
OTP Program (OTPP)................................................... 40
Read OTP Data Bytes (OTPR) ..................................... 40
OTP Regions
............................................................... 41
Programming OTP Address Space............................... 41
Reading OTP Data ....................................................... 41
Locking OTP Regions................................................... 42
Power-up and Power-down........................................
44
Initial Delivery State....................................................
45
8.
9.
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
9.12
9.13
9.14
9.15
9.16
9.17
9.18
Sector Address Table
................................................ 16
Command Definitions................................................
Read Data Bytes (READ) ............................................
Read Data Bytes at Higher Speed
(FAST_READ) .............................................................
Dual Output Read Mode (DOR)...................................
Quad Output Read Mode (QOR) .................................
DUAL I/O High Performance Read
Mode (DIOR)................................................................
Quad I/O High Performance Read
Mode (QIOR) ...............................................................
Read Identification (RDID) ...........................................
Read-ID (READ_ID).....................................................
Write Enable (WREN) ..................................................
Write Disable (WRDI)...................................................
Read Status Register (RDSR) .....................................
Read Configuration Register (RCR) ............................
Write Registers (WRR) ................................................
Page Program (PP)......................................................
QUAD Page Program (QPP) .......................................
Parameter Sector Erase (P4E, P8E) ...........................
Sector Erase (SE) ........................................................
Bulk Erase (BE) ...........................................................
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21
21
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23
25
28
29
29
30
31
32
33
35
36
37
37
Document Number: 002-00650 Rev. *L
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Device Operations
.....................................................
Byte or Page Programming..........................................
Quad Page Programming ............................................
Dual and Quad I/O Mode .............................................
Sector Erase / Bulk Erase............................................
Monitoring Write Operations
Using the Status Register ............................................
7.6 Active Power and Standby Power Modes....................
7.7 Status Register ............................................................
7.8 Configuration Register .................................................
7.9 Data Protection Modes ................................................
7.10 Hold Mode (HOLD#) ....................................................
7.11 Accelerated Programming Operation...........................
15.
16.
17.
Operating Ranges
....................................................... 47
18. AC Characteristics......................................................
49
18.1 Capacitance .................................................................. 50
19. Physical Dimensions
.................................................. 52
19.1 SOC008 wide — 8-pin Plastic Small
Outline Package (208-mils Body Width) ....................... 52
19.2 SO3 016 — 16-pin Wide Plastic Small
Outline Package (300-mils Body Width) ....................... 53
19.3 UNE008 — USON 8-contact (5 x 6 mm)
No-Lead Package ......................................................... 54
19.4 WNF008 — WSON 8-contact (6 x 8 mm)
No-Lead Package ......................................................... 55
19.5 FAB024 — 24-ball Ball Grid Array
(6 x 8 mm) Package...................................................... 56
19.6 FAC024 — 24-ball Ball Grid Array
(6 x 8 mm) Package...................................................... 57
20. Revision History..........................................................
58
Document History Page ..................................................... 58
Sales, Solutions, and Legal Information .......................... 60
Worldwide Sales and Design Support ........................... 60
Products ........................................................................ 60
PSoC® Solutions .......................................................... 60
Cypress Developer Community ..................................... 60
Technical Support ......................................................... 60
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DC Characteristics......................................................
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46
14.1 Absolute Maximum Ratings .......................................... 46
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Program Acceleration via W#/ACC Pin.....................
45
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S25FL032P
1. Block Diagram
SRAM
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DATA PATH
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W# / ACC / IO2
SI / IO0
SO / IO1
GND
V
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HOLD# / IO3
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S25FL032P
2. Connection Diagrams
Figure 1. 16-pin Plastic Small Outline Package (SO)
HOLD#/IO3
VCC
DNC
DNC
DNC
DNC
CS#
SO/IO1
Note
DNC = Do Not Connect (Reserved for future use)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SCK
SI/IO0
DNC
DNC
DNC
DNC
GND
W#/ACC/IO2
Figure 2. 8-pin Plastic Small Outline Package (SO)
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W#/ACC/IO2
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1
2
USON
CS#
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Figure 3. 8-contact USON (5 x 6 mm) Package
CS#
SO/IO1
W#/ACC/IO2
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Note
There is an exposed central pad on the underside of the USON package. This should not be connected to any voltage or signal line on the PCB. Connecting the central
pad to GND (V
SS
) is possible, provided PCB routing ensures 0mV difference between voltage at the USON GND (V
SS
) lead and the central exposed pad.
Figure 4. 8-contact WSON Package (6 x 8 mm)
CS#
SO/IO1
W#/ACC/IO2
GND
1
2
WSON
3
4
Note
There is an exposed central pad on the underside of the WSON package. This should not be connected to any voltage or signal line on the PCB. Connecting the central
pad to GND (V
SS
) is possible, provided PCB routing ensures 0mV difference between voltage at the WSON GND (V
SS
) lead and the central exposed pad.
Document Number: 002-00650 Rev. *L
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VCC
SCK
SI/IO0
VCC
SCK
SI/IO0
VCC
SCK
SI/IO0
HOLD#/IO3
HOLD#/IO3
HOLD#/IO3
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