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CONTINUITY OF SPECIFICATIONS
There is no change to this document as a result of offering the device as a Cypress product. Any changes that have been made
are the result of normal document improvements and are noted in the document history page, where supported. Future revisions
will occur when appropriate, and changes will be noted in a document history page.
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this document.
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Cypress Semiconductor Corporation
Document Number: 002-00722 Rev. *H
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 09, 2017
S25FL204K
4-Mbit 3.0 V SPI Flash Memory
Distinctive Features
Single power supply operation
– Full voltage range: 2.7 to 3.6V
4-Mbit Serial Flash
– 4-Mbit/512 kbyte/2048 pages
– 256 bytes per programmable page
– Uniform 4-kbyte Sectors/64-kbyte Blocks
Standard and Dual
– Standard SPI: SCK, CS#, SI, SO, WP#, HOLD#
– Dual SPI: SCK, CS#, SI/IO0, SO, WP#, HOLD#
– Fast Read Dual Output instruction
– Auto-increment Read capability
High Performance
– FAST READ (Serial): 85 MHz clock rate
– DUAL OUTPUT READ: 85 MHz clock rate
Low Power Consumption
– 12 mA typical active current
– 15 µA typical standby current
Flexible Architecture with 4 kB Sectors
– Sector Erase (4 kB)
– Block Erase (64 kB)
– Page Program up to 256 bytes
– 100k erase/program cycles typical
– 20-year data retention typical
Software and Hardware Write Protection
– Write Protect all or portion of memory via software
– Enable/Disable protection with WP# pin
High Performance Program/Erase Speed
– Page program time: 1.5 ms typical
– Sector erase time (4 kB): 50 ms typical
– Block erase time (64 kB): 500 ms typical
– Chip erase time: 3.5 seconds typical
Package Options
– 8-pin SOIC 150/208-mil
– All Pb-free packages are RoHS compliant
The S25FL204K (4-Mbit, 512-kbyte) Serial Flash memory, with advanced write protection mechanisms. TheS25FL204K supports
the standard Serial Peripheral Interface (SPI), and a high performance Dual output using SPI pins: Serial Clock, Chip Select, Serial
SI/IO0, SO, WP# and HOLD#. SPI clock frequencies of up to 85 MHz are supported along with a clock rate of
85 MHz for Dual Output Read.
The S25FL204K array is organized into 2048 programmable pages of 256 bytes each. Up to 256 bytes can be programmed at a
time. Pages can be erased in groups of 16 (4 kB Sector Erase), groups of 256 (64 kB Block Erase) or the entire chip (Chip Erase).
The S25FL204K has128 erasable sectors and 8 erasable blocks. The small 4 kB sectors allow for greater flexibility in applications
that require data and parameter storage.
A Hold pin, Write Protect Pin and programmable write protection provide further control flexibility. Additionally, the S25FL204K
device supports JEDEC standard manufacturer and device identification.
General Description
Cypress Semiconductor Corporation
Document Number: 002-00722 Rev. *H
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 09, 2017
S25FL204K
Table of Contents
Distinctive Features
............................................................. 2
General Description
............................................................. 2
1.
2.
3.
4.
4.1
5.
6.
6.1
6.2
6.3
6.4
7.
7.1
7.2
7.3
7.4
8.
8.1
8.2
Block Diagram..............................................................
4
Connection Diagrams..................................................
4
Signal Descriptions
..................................................... 5
Ordering Information
................................................... 6
Valid Combinations ........................................................ 6
Memory Organizations
................................................ 7
Functional Description
................................................
SPI Modes .....................................................................
Dual Output SPI .............................................................
Hold Function.................................................................
Status Register ..............................................................
8
8
8
8
9
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.15
9.
9.1
9.2
9.3
9.4
9.5
9.6
Read Status Register (05h) .......................................... 13
Write Status Register (01h)........................................... 14
Read Data (03h) ........................................................... 15
Fast Read (0Bh) ........................................................... 15
Fast Read Dual Output (3Bh) ....................................... 16
Page Program (PP) (02h) ............................................. 17
Sector Erase (SE) (20h)................................................ 18
Block Erase (BE) (D8h)................................................. 19
Chip Erase (CE) (C7h).................................................. 19
Deep Power-down (DP) (B9h) ...................................... 20
Release Deep Power-down / Device ID (ABh) ............. 21
Read Manufacturer / Device ID (90h) ........................... 22
Read Identification (RDID) (9Fh) .................................. 23
Electrical Specifications.............................................
25
Power-up Timing........................................................... 25
Absolute Maximum Ratings .......................................... 26
Recommended Operating Ranges ............................... 26
DC Characteristics ........................................................ 27
AC Measurement Conditions ........................................ 27
AC Characteristics ........................................................ 28
Write Protection
......................................................... 10
Page Programming ...................................................... 11
Sector Erase, Block Erase, and Chip Erase ................ 11
Polling During a Write, Program, or Erase Cycle......... 11
Active Power, Stand-by Power, and Deep
Power-Down Modes ..................................................... 11
Commands
................................................................. 11
Write Enable (06h) ....................................................... 12
Write Disable (04h) ...................................................... 13
10. Package Material.........................................................
31
10.1 8-Pin SOIC 150-mil Package (SOA 008) ...................... 31
10.2 8-Pin SOIC 208-mil Package (SOC 008)...................... 32
11.
Revision History..........................................................
33
Document Number: 002-00722 Rev. *H
Page 3 of 35
S25FL204K
1. Block Diagram
X -Decoder
Address
Buffers
and
Latches
Flash
M em ory
Y- Decoder
Control Logic
I/O Buffers
and Data
Latches
Serial Interface
CS #
SCK
SI/IO0
SO
W P#
HO LD #
2. Connection Diagrams
Figure 2.1
8-pin SOIC (150/208 mil)
CS#
SO
WP#
GND
1
2
3
4
8
7
6
5
VCC
HOLD#
SCK
SI/IO0
Document Number: 002-00722 Rev. *H
Page 4 of 35
S25FL204K
3. Signal Descriptions
Serial Data Input / Output (SI/IO0)
The SPI Serial Data Input/Output (SI/IO0) pin provides a means for instructions, addresses and data to be serially written to (shifted
into) the device. Data is latched on the rising edge of the Serial Clock (SCK) input pin. The SI/IO0 pin is also used as an output pin
when the Fast Read Dual Output instruction is executed.
Serial Data Output (SO)
The SPI Serial Data Output (SO) pin provides a means for data and status to be serially read from (shifted out of) the device. Data is
shifted out on the falling edge of the Serial Clock (SCK) input pin.
Serial Clock (SCK)
The SPI Serial Clock Input (SCK) pin provides the timing for serial input and output operations.
See
SPI Modes
on page 8.
Chip Select (CS#)
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is deselected and the Serial
Data Output pins are at high impedance.
When deselected, the device’s power consumption will be at standby levels unless an internal erase, program or status register
cycle is in progress. When CS# is brought low the device will be selected, power consumption will increase to active levels and
instructions can be written to and data read from the device. After power-up, CS# must transition from high to low before a new
instruction will be accepted.
HOLD (HOLD#)
The HOLD# pin allows the device to be paused while it is actively selected. When HOLD# is brought low, while CS# is low, the SO
pin will be at high impedance and signals on the SI and SCK pins will be ignored (don’t care). The HOLD# function can be useful
when multiple devices are sharing the same SPI signals.
Write Protect (WP#)
The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status
Register’s Block Protect (BP0, BP1 and BP2, BP3) bits and Status Register Protect (SRP) bits, a portion or the entire memory array
can be hardware protected.
Table 3.1
Pin Descriptions
Symbol
SCK
SI/IO0
SO
CS#
WP#
HOLD#
VCC
GND
Note:
1. SI/IO0 output is used for Dual Output Read instruction.
Pin Name
Serial Clock Input
Serial Data Input / Output
(1)
Serial Data Output
Chip Enable
Write Protect
Hold Input
Supply Voltage (2.7-3.6V)
Ground
Document Number: 002-00722 Rev. *H
Page 5 of 35
