S25FS512S
512 Mbit, 1.8 V Serial Peripheral Interface
with Multi-I/O Flash
Features
Serial Peripheral Interface (SPI) with Multi-I/O
– SPI Clock polarity and phase modes 0 and 3
– Double Data Rate (DDR) option
– Extended Addressing – 24 or 32-bit address options
– Serial Command subset and footprint compatible with
S25FL-A, S25FL-K, S25FL-P, and S25FL-S SPI families
– Multi I/O Command subset and footprint compatible with
S25FL-P, and S25FL-S SPI families
Read
– Commands: Normal, Fast, Dual I/O, Quad I/O, DDR Quad
I/O
– Modes: Burst Wrap, Continuous (XIP), QPI
– Serial Flash Discoverable Parameters (SFDP) and
Common Flash Interface (CFI), for configuration
information.
Program
– 256 or 512 Bytes Page Programming buffer
– Program suspend and resume
– Automatic Error Checking and Correction (ECC) – internal
hardware ECC with single bit error correction
Erase
– Hybrid sector option
– Physical set of eight 4-kbytes sectors and one
224-kbytes sector at the top or bottom of address
space with all remaining sectors of 256 kbytes
– Uniform sector option
– Uniform 256 kbyte blocks
– Erase suspend and resume
– Erase status evaluation
– 100,000 Program-Erase Cycles
– 20 Year Data Retention
Security Features
– One Time Program (OTP) array of 1024 bytes
– Block Protection:
– Status Register bits to control protection against
program or erase of a contiguous range of sectors.
– Hardware and software control options
– Advanced Sector Protection (ASP)
– Individual sector protection controlled by boot code or
password
– Option for password control of read access
Technology
– Cypress 65-nm MirrorBit Technology with Eclipse
Architecture
Supply Voltage
– 1.7 V to 2.0 V
Temperature Range / Grade
– Industrial (40 °C to +85 °C)
– Industrial Plus (40 °C to +105 °C)
– Extended (40 °C to +125 °C)
– Automotive, AEC-Q100 Grade 3 (40 °C to +85 °C)
– Automotive, AEC-Q100 Grade 2 (40 °C to +105 °C)
– Automotive, AEC-Q100 Grade 1 (40 °C to +125 °C)
Packages (all Pb-free)
– 16-lead SOIC 300 mil (SO3016)
– WSON 6x8 mm (WNH008)
– BGA-24 6
8 mm
– 5
5 ball (FAB024) footprint
– Known Good Die and Known Tested Die
Cypress Semiconductor Corporation
Document Number: 002-00488 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 03, 2016
S25FS512S
Performance Summary
Maximum Read Rates
Command
Read
Fast Read
Dual Read
Quad Read
DDR Quad I/O Read
Clock Rate (MHz)
50
133
133
133
80
Mbytes/s
6.25
16.5
33
66
80
Typical Program and Erase Rates
Operation
Page Programming (256-bytes page buffer)
Page Programming (512-bytes page buffer)
4-kbytes Physical Sector Erase (Hybrid Sector Option)
256-kbytes Sector Erase (Uniform Logical Sector Option)
kbytes/s
712
1080
28
250
Typical Current Consumption,
40°C
to +85°C
Operation
Serial Read 50 MHz
Serial Read 133 MHz
Quad Read 133 MHz
Quad DDR Read 80 MHz
Program
Erase
Standby
Deep Power Down
Current (mA)
10
20
60
70
60
60
0.07
0.006
Document Number: 002-00488 Rev. *E
Page 2 of 143
S25FS512S
Contents
1.
1.1
1.2
1.3
1.4
2.
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
3.
3.1
3.2
3.3
3.4
3.5
4.
4.1
4.2
4.3
4.4
4.5
4.6
5.
5.1
5.2
5.3
5.4
5.5
6.
6.1
6.2
Overview
.......................................................................
General Description .......................................................
Migration Notes..............................................................
Glossary.........................................................................
Other Resources............................................................
4
4
4
7
7
6.3
7.
7.1
7.2
7.3
7.4
7.5
7.6
8.
8.1
8.2
8.3
8.4
8.5
9.
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
10.
11.
11.1
11.2
11.3
BGA 24-Ball, 5x5 Ball Footprint (FAB024).................... 43
Address Space Maps
.................................................. 45
Overview....................................................................... 45
Flash Memory Array...................................................... 45
ID-CFI Address Space .................................................. 46
JEDEC JESD216 Serial Flash
Discoverable Parameters (SFDP) Space ..................... 46
OTP Address Space ..................................................... 47
Registers....................................................................... 48
Data Protection
........................................................... 65
Secure Silicon Region (OTP)........................................ 65
Write Enable Command................................................ 66
Block Protection ............................................................ 66
Advanced Sector Protection ......................................... 67
Recommended Protection Process .............................. 73
Commands
.................................................................. 74
Command Set Summary............................................... 75
Identification Commands .............................................. 80
Register Access Commands......................................... 83
Read Memory Array Commands .................................. 94
Program Flash Array Commands ............................... 102
Erase Flash Array Commands.................................... 104
One Time Program Array Commands ........................ 111
Advanced Sector Protection Commands .................... 111
Reset Commands ....................................................... 117
DPD Commands ......................................................... 119
Embedded Algorithm Performance Tables
............ 121
Software Interface
Hardware Interface
Signal Descriptions
..................................................... 8
Input/Output Summary................................................... 8
Multiple Input / Output (MIO).......................................... 9
Serial Clock (SCK) ......................................................... 9
Chip Select (CS#) .......................................................... 9
Serial Input (SI) / IO0 ..................................................... 9
Serial Output (SO) / IO1................................................. 9
Write Protect (WP#) / IO2 ............................................ 10
IO3 / RESET# ............................................................. 10
Voltage Supply (V
DD
)................................................... 10
Supply and Signal Ground (V
SS
) ................................. 10
Not Connected (NC) .................................................... 11
Reserved for Future Use (RFU)................................... 11
Do Not Use (DNU) ....................................................... 11
Block Diagrams............................................................ 12
Signal Protocols.........................................................
SPI Clock Modes .........................................................
Command Protocol ......................................................
Interface States............................................................
Configuration Register Effects on the Interface ...........
Data Protection ............................................................
Electrical Specifications............................................
Absolute Maximum Ratings .........................................
Thermal Resistance .....................................................
Latchup Characteristics ...............................................
Operating Ranges........................................................
Power-Up and Power-Down ........................................
DC Characteristics .......................................................
Timing Specifications
................................................
Key to Switching Waveforms .......................................
AC Test Conditions ......................................................
Reset............................................................................
SDR AC Characteristics...............................................
DDR AC Characteristics. .............................................
14
14
15
19
23
23
24
24
24
24
24
25
27
30
30
30
31
34
36
Data Integrity
............................................................. 121
Erase Endurance ........................................................ 121
Data Retention ............................................................ 121
Serial Flash Discoverable Parameters
(SFDP) Address Map.................................................. 122
11.4 Device ID and Common Flash Interface
(ID-CFI) Address Map................................................. 124
11.5 Initial Delivery State .................................................... 138
Ordering Information
12.
13.
14.
Ordering Part Number
.............................................. 139
Contact.......................................................................
140
Revision History........................................................
141
Physical Interface
...................................................... 39
SOIC 16-Lead Package ............................................... 39
8-Connector Package .................................................. 41
Document Number: 002-00488 Rev. *E
Page 3 of 143
S25FS512S
1. Overview
1.1
General Description
The Cypress S25FS512S device is a flash non-volatile memory product using:
MirrorBit technology — that stores two data bits in each memory array transistor
Eclipse architecture — that dramatically improves program and erase performance
65 nm process lithography
The S25FS512S connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output
(Single I/O or SIO) is supported as well as optional two-bit (Dual I/O or DIO) and four-bit wide Quad I/O (QIO) or Quad Peripheral
Interface (QPI) serial commands. This multiple-width interface is called SPI Multi-I/O or MIO. In addition, there are Double Data Rate
(DDR) read commands for QIO and QPI that transfer address and read data on both edges of the clock.
The FS-S Eclipse architecture features a Page Programming Buffer that allows up to 512 bytes to be programmed in one operation,
resulting in faster effective programming and erase than prior generation SPI program or erase algorithms.
Executing code directly from flash memory is often called Execute-In-Place or XIP. By using S25FS512S devices at the higher clock
rates supported, with Quad or DDR-Quad commands, the instruction read transfer rate can match or exceed traditional parallel
interface, asynchronous, NOR flash memories, while reducing signal count dramatically.
The S25FS512S products offer high densities coupled with the flexibility and fast performance required by a variety of mobile or
embedded applications. They are an excellent solution for systems with limited space, signal connections, and power. They are ideal
for code shadowing to RAM, executing code directly (XIP), and storing reprogrammable data.
1.2
1.2.1
Migration Notes
Features Comparison
The S25FS512S is command subset and footprint compatible with prior generation FL-S, FL-K, and FL-P families. However, the
power supply and interface voltages are nominal 1.8V.
Table 1.1
Cypress SPI Families Comparison
Parameter
Technology Node
Architecture
Density
Bus Width
Supply Voltage
Normal Read Speed (SDR)
Fast Read Speed (SDR)
Dual Read Speed (SDR)
Quad Read Speed (SDR)
Quad Read Speed (DDR)
Program Buffer Size
Erase Sector Size
Parameter Sector Size
Sector Erase Rate (typ.)
Page Programming Rate
(typ.)
OTP
FS-S
65 nm
MirrorBit
®
Eclipse
™
128 Mb - 512 Mb
x1, x2, x4
1.7V - 2.0V
6 MB/s (50 MHz)
16.5 MB/s (133 MHz)
33 MB/s (133 MHz)
66 MB/s (133 MHz)
80 MB/s (80 MHz)
256B / 512B
64 kB / 256 kB
4 kB (option)
500 kB/s
0.71 MB/s (256B)
1.08 MB/s (512B)
1024B
FL-S
65 nm
MirrorBit
®
Eclipse
™
128 Mb - 1 Gb
x1, x2, x4
2.7V - 3.6V / 1.65V - 3.6V V
IO
6 MB/s (50 MHz)
17 MB/s (133 MHz)
26 MB/s (104 MHz)
52 MB/s (104 MHz)
80 MB/s (80 MHz)
256B / 512B
64 kB / 256 kB
4 kB (option)
500 kB/s
1.2 MB/s (256B)
1.5 MB/s (512B)
1024B
FL-K
90 nm
Floating Gate
4 Mb - 128 Mb
x1, x2, x4
2.7V - 3.6V
6 MB/s (50 MHz)
13 MB/s (104 MHz)
26 MB/s (104 MHz)
52 MB/s (104 MHz)
—
256B
4 kB / 32 kB / 64 kB
4 kB
136 kB/s (4 kB)
437 kB/s (64 kB)
365 kB/s
768B (3x256B)
FL-P
90 nm
MirrorBit
®
32 Mb - 256 Mb
x1, x2, x4
2.7V - 3.6V
5 MB/s (40 MHz)
13 MB/s (104 MHz)
20 MB/s (80 MHz)
40 MB/s (80 MHz)
—
256B
64 kB / 256 kB
4 kB
130 kB/s
170 kB/s
506B
Document Number: 002-00488 Rev. *E
Page 4 of 143
S25FS512S
Table 1.1
Cypress SPI Families Comparison (Continued)
Parameter
Advanced Sector Protection
Auto Boot Mode
Erase Suspend/Resume
Program Suspend/Resume
Deep Power-Down Mode
Operating Temperature
FS-S
Yes
No
Yes
Yes
Yes
-40°C to +85°C / +105°C
FL-S
Yes
Yes
Yes
Yes
No
-40°C to +85°C / +105°C / +125°C
FL-K
No
No
Yes
Yes
Yes
-40°C to +85°C
FL-P
No
No
No
No
Yes
-40°C to +85°C / +105°C
Notes:
1. 256B program page option only for 128 Mb and 256 Mb density FL-S devices.
2. FL-P column indicates FL129P MIO SPI device (for 128 Mb density), FL128P does not support MIO, OTP, or 4 kB sectors.
3. 64-kB sector erase option only for 128 Mb / 256 Mb density FL-P, FL-S, and FS-S devices.
4. FL-K family devices can erase 4-kB sectors in groups of 32 kB or 64 kB.
5. Only 128 Mb/256 Mb density FL-S devices have 4-kB parameter sector option.
6. 512 Mb / 1 Gb FL-S devices support 256 kB-sector only.
7. The FS512 device does not support 64 kB-sectors.
8. Refer to individual product data sheets for further details.
1.2.2
1.2.2.1
Known Differences from Prior Generations
Error Reporting
FL-K and FL-P memories either do not have error status bits or do not set them if program or erase is attempted on a protected
sector. The FS-S and FL-S families do have error reporting status bits for program and erase operations. These can be set when
there is an internal failure to program or erase, or when there is an attempt to program or erase a protected sector. In these cases
the program or erase operation did not complete as requested by the command. The P_ERR or E_ERR bits and the WIP bit will be
set to and remain 1 in SR1V. The clear status register command must be sent to clear the errors and return the device to standby
state.
1.2.2.2
Secure Silicon Region (OTP)
The FS-S size and format (address map) of the One Time Program area is different from FL-K and FL-P generations. The method
for protecting each portion of the OTP area is different. For additional details see
Secure Silicon Region (OTP)
on page 65.
1.2.2.3
Configuration Register Freeze Bit
The Configuration Register 1 Freeze Bit CR1V[0], locks the state of the Block Protection bits (SR1NV[4:2] and SR1V[4:2]),
TBPARM_O bit (CR1NV[2]), and TBPROT_O bit (CR1NV[5]), as in prior generations. In the FS-S and FL-S families the Freeze Bit
also locks the state of the Configuration Register 1 BPNV_O bit (CR1NV[3]), and the Secure Silicon Region (OTP) area.
1.2.2.4
Sector Erase Commands
The command for erasing a 4-kbytes sector is supported only for use on 4-kbytes parameter sectors at the top or bottom of the FS-
S device address space.
The command for erasing an 8-kbyte area (two 4-kbytes sectors) is not supported.
The command for erasing a 32-kbyte area (eight 4-kbytes sectors) is not supported.
The 64 kbytes erase command is not supported for the 512 Mbits density FS-S device.
1.2.2.5
Deep Power-Down
A Deep Power-Down (DPD) function is supported in the FS-S family devices.
Document Number: 002-00488 Rev. *E
Page 5 of 143
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