S29AL016M
16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
3.0 Volt-only Boot Sector Flash Memory
featuring MirrorBit
TM
technology
Data Sheet
DATASHEET
Distinctive Characteristics
Architectural Advantages
Single power supply operation
— 3 V for read, erase, and program operations
Manufactured on 0.23 µm MirrorBit
TM
process
technology
SecSi
TM
(Secured Silicon) Sector region
— 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
— May be programmed and locked at the factory or by
the customer
Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-
one 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and thirty-
one 32 Kword sectors (word mode)
Compatibility with JEDEC standards
— Provides pinout and software compatibility for single-
power supply flash, and superior inadvertent write
protection
Top or bottom boot block configurations available
100,000 erase cycle typical per sector
20-year typical data retention
— 400 nA standby mode current
— 15 mA read current
— 40 mA program/erase current
— 400 nA Automatic Sleep mode current
Package options
— 48-ball Fine-pitch BGA
— 64-ball Fortified BGA
— 48-pin TSOP
Software Features
— Program Suspend & Resume: read other sectors
before programming operation is completed
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall
multiple-word programming time
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
Hardware Features
— Sector Protection: hardware-level method of
preventing write operations within a sector
— Temporary Sector Unprotect: V
ID
-level method of
changing code in locked sectors
— Hardware reset input (RESET#) resets device
— Ready/Busy# output (RY/BY#) indicates program or
erase cycle completion
Performance Characteristics
High performance
— 90 ns access time
— 0.7 s typical sector erase time
Low power consumption (typical values at 5 MHz)
Publication Number
S29AL016M_00
Revision
A
Amendment
4
Issue Date
April 21, 2004
General Description
The S29AL016M is a 16 Mbit, 3.0 Volt-only Flash memory organized as 2,097,152
bytes or 1,048,576 words. The device is offered in a 48-ball Fine-pitch BGA, 64-
ball Fortified BGA, and 48-pin TSOP packages. The word-wide data (x16) appears
on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. The device re-
quires only a
single 3.0 volt power supply
for both read and write functions,
designed to be programmed in-system with the standard system 3.0 volt V
CC
sup-
ply. The device can also be programmed in standard EPROM programmers.
The device offers access times of 90 and 100 ns. To eliminate bus contention the
device has separate chip enable (CE#), write enable (WE#) and output enable
(OE#) controls.
The device is entirely command set compatible with the
JEDEC single-power-
supply Flash standard.
Commands are written to the device using standard
microprocessor write timing. Write cycles also internally latch addresses and data
needed for the programming and erase operations.
The
sector erase architecture
allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through command sequences.
Once a program or erase operation has begun, the host system need only poll
the DQ7 (Data# Polling) or DQ6 (toggle)
status bits
or monitor the
Ready/
Busy# (RY/BY#)
output to determine whether the operation is complete. To
facilitate programming, an
Unlock Bypass
mode reduces command sequence
overhead by requiring only two write cycles to program data instead of four.
Hardware data protection
measures include a low V
CC
detector that automati-
cally inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase operations in any combina-
tion of sectors of memory. This can be achieved in-system or via programming
equipment.
The
Erase Suspend/Erase Resume
feature allows the host system to pause an
erase operation in a given sector to read or program any other sector and then
complete the erase operation. The
Program Suspend/Program Resume
fea-
ture enables the host system to pause a program operation in a given sector to
read any other sector and then complete the program operation.
The
hardware RESET# pin
terminates any operation in progress and resets the
device, after which it is then ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would thus also reset the de-
vice, enabling the host system to read boot-up firmware from the Flash memory
device.
The device reduces power consumption in the
standby mode
when it detects
specific voltage levels on CE# and RESET#, or when addresses have been stable
for a specified period of time.
The
SecSi™ (Secured Silicon) Sector
provides a 128-word/256-byte area for
code or data that can be permanently protected. Once this sector is protected, no
further changes within the sector can occur.
MirrorBit flash technology combines years of Flash memory manufacturing expe-
rience to produce the highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector simultaneously via hot-hole
assisted erase. The data is programmed using hot electron injection.
3
S29AL016M
S29AL016M_00A4 April 21, 2004
Table of Contents
S29AL016M 2
General Description 3
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 10
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 11
Table 1. S29AL016M Device Bus Operations .........................11
Figure 5. Erase Operation .................................................. 30
Program Suspend/Program Resume Command Sequence ...... 30
Figure 6. Program Suspend/Program Resume ....................... 31
Command Definitions Tables ........................................................... 32
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 34
DQ7: Data# Polling .............................................................................. 34
RY/BY#: Ready/Busy# ..........................................................................35
DQ6: Toggle Bit I .................................................................................. 36
DQ2: Toggle Bit II ................................................................................ 36
Reading Toggle Bits DQ6/DQ2 .........................................................37
Figure 8. Toggle Bit Algorithm ............................................ 38
Command Definitions (x16 Mode, BYTE# = V
IH
).................... 32
Command Definitions (x8 Mode, BYTE# = V
IL
)...................... 33
Figure 7. Data# Polling Algorithm ....................................... 35
Word/Byte Configuration .................................................................... 11
Requirements for Reading Array Data ............................................ 11
Writing Commands/Command Sequences ................................... 12
Program and Erase Operation Status .............................................. 12
Standby Mode ......................................................................................... 12
Automatic Sleep Mode ......................................................................... 13
RESET#: Hardware Reset Pin ............................................................ 13
Output Disable Mode ........................................................................... 13
Table 2. Sector Address Tables (Model 01, Top Boot Device) ...14
Table 3. Sector Address Tables (Model 02, Bottom Boot Device) .
15
DQ5: Exceeded Timing Limits .......................................................... 38
DQ3: Sector Erase Timer .................................................................. 39
Table 12. Write Operation Status ....................................... 39
Absolute Maximum Ratings . . . . . . . . . . . . . . . . .40
Figure 9. Maximum Negative Overshoot Waveform................ 40
Figure 10. Maximum Positive Overshoot Waveform................ 40
Autoselect Mode ................................................................................... 15
Table 4. Autoselect Codes (High Voltage Method) ..................16
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 40
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 41
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Figure 11. Test Setup ........................................................ 42
Table 13. Test Specifications ............................................. 42
Figure 12. Input Waveforms and Measurement Levels............ 42
Sector Protection/Unprotection ....................................................... 16
Temporary Sector Unprotect ........................................................... 17
Figure 1. Temporary Sector Unprotect Operation................... 17
Figure 2. In-System Single High Voltage Sector Protect/
Unprotect Algorithms ........................................................ 18
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 43
Read Operations ................................................................................... 43
Figure 13. Read Operations Timings .................................... 43
SecSi (Secured Silicon) Sector Flash Memory Region ................ 19
Table 5. SecSi Sector Addressing ........................................19
Hardware Reset (RESET#) ................................................................ 44
Figure 14. RESET# Timings ................................................ 44
Customer Lockable: SecSi Sector NOT Programmed or Pro-
tected At the Factory ........................................................................... 19
Figure 3. SecSi Sector Protect Verify ................................... 20
Erase/Program Operations ................................................................ 45
Figure 15. Program Operation Timings ................................. 46
Figure 16. Chip/Sector Erase Operation Timings.................... 47
Figure 17. Data# Polling Timings
(During Embedded Algorithms)........................................... 48
Figure 18. Toggle Bit Timings
(During Embedded Algorithms)........................................... 48
Figure 19. DQ2 vs. DQ6 for Erase and
Erase Suspend Operations ................................................. 49
Figure 20. Temporary Sector Unprotect/Timing Diagram ........ 49
Figure 21. Sector Protect/Unprotect Timing Diagram.............. 50
Figure 22. Alternate CE# Controlled Write Operation Timings.. 52
Common Flash Memory Interface (CFI) .......................................20
Table 6. CFI Query Identification String ...............................21
Table 7. System Interface String .........................................22
Table 8. Device Geometry Definition ....................................22
Table 9. Primary Vendor-Specific Extended Query .................23
Hardware Data Protection ................................................................ 23
Low V
CC
Write Inhibit ....................................................................... 23
Write Pulse “Glitch” Protection ...................................................... 23
Logical Inhibit ......................................................................................... 24
Power-Up Write Inhibit ..................................................................... 24
Command Definitions . . . . . . . . . . . . . . . . . . . . . .24
Reading Array Data ............................................................................. 24
Reset Command ................................................................................... 24
Autoselect Command Sequence ...................................................... 25
Word/Byte Program Command Sequence ................................... 25
Unlock Bypass Command Sequence ............................................... 26
Figure 4. Program Operation .............................................. 27
Chip Erase Command Sequence ...................................................... 27
Sector Erase Command Sequence ..................................................28
Erase Suspend/Erase Resume Commands ....................................28
Erase and Programming Performance . . . . . . . . . 53
TSOP Pin and BGA Package Capacitance . . . . . 53
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 54
TS 048—48-Pin Standard TSOP ...................................................... 54
TSR048—48-Pin Reverse TSOP ...................................................... 55
FBA048—48-Ball Fine-Pitch Ball Grid Array (BGA)
6 x 8 mm Package ................................................................................. 56
LAA064—64-Ball Fortified Ball Grid Array (BGA)
13 x 11 mm Package ............................................................................... 57
Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . 58
April 21, 2004 S29AL016M_00A4
S29AL016M
4
Product Selector Guide
Family Part Number
Speed Option
Max access time (ns)
Max CE# access time (ns)
Max OE# access time (ns)
Notes:
1. See
“AC Characteristics”
for full specifications.
2. Contact sales office or representative for availability and ordering information.
S29AL016M
Full Voltage Range: V
CC
= 2.7–3.6 V
90
90
90
25
100
100
100
25
Block Diagram
RY/BY#
V
CC
V
SS
RESET#
Sector Switches
Erase Voltage
Generator
Input/Output
Buffers
DQ15–DQ0 (A-1)
WE#
BYTE#
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data
Latch
CE#
OE#
STB
V
CC
Detector
Address Latch
Y-Decoder
Y-Gating
Timer
X-Decoder
Cell Matrix
A19–A0
5
S29AL016M
S29AL016M_00A4 April 21, 2004
Connection Diagrams
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
Standard TSOP
April 21, 2004 S29AL016M_00A4
S29AL016M
6
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