S29CD032J
S29CD016J
S29CL032J
S29CL016J
32/16 Mbit, 2.6/3.3 V, Dual Boot,
Simultaneous Read/Write, Burst Flash
General Description
The Spansion S29CD-J and S29CL-J devices are Floating Gate products fabricated in 110-nm process technology. These burst-
mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks,
using separate data and address pins. These products can operate up to 75 MHz (32 Mb) or 66 MHz (16 Mb), and use a single V
CC
of 2.5V to 2.75V (S29CD-J) or 3.0V to 3.6V (S29CL-J) that make them ideal for today’s demanding automotive applications.
Distinctive Characteristics
110 nm Floating Gate Technology
Single 2.6V (S29CD-J) or 3.3V (S29CL-J) for read/program/erase
Simultaneous Read/Write operation with zero latency
x32 Data Bus
Dual Boot Sector Configuration (top and bottom)
Flexible Sector Architecture
– CD016J and CL016J: Eight 2k Double word, Thirty 16k Double
word, and Eight 2k Double Word sectors
– CD032J and CL032J: Eight 2k Double word, Sixty-two 16k
Double Word, and Eight 2k Double Word sectors
VersatileI/O™ control (1.65V to 3.6V)
Programmable Burst Interface
– Linear for 2, 4, and 8 double word burst with wrap around
Secured Silicon Sector that can be either factory or customer locked
20 year data retention (typical)
Cycling Endurance: 1 million write cycles per sector (typical)
Command set compatible with JEDEC (JC42.4) standard
Supports Common Flash Interface (CFI)
Extended Temperature range
Persistent and Password methods of Advanced Sector Protection
Unlock Bypass program command to reduce programming time
ACC input pin to reduce factory programming time
Data Polling bits indicate program and erase operation completion
Hardware (WP#) protection of two outermost sectors in the large
bank
Ready/Busy (RY/BY#) output indicates data available to system
Suspend and Resume commands for Program and Erase Operation
Offered Packages
– 80-pin PQFP
– 80-ball Fortified BGA (13 x 11 mm and 11 x 9mm versions)
– Pb-free package option available
– Known Good Die
Performance Characteristics
Read Access Times
Speed Option (MHz)
Max Asynch. Access Time, ns (t
ACC
)
Max Synch. Burst Access, ns (t
BACC
)
Min Initial Clock Delay (clock cycles)
Max CE# Access Time, ns (t
CE
)
Max OE# Access time, ns (t
OE
)
75
(32 Mb only)
54
8
5
54
20
66
54
8
5
54
20
56
54
8
5
54
20
40
54
8
4
54
20
Typical Program and Erase Times
Double Word Programming
Sector Erase
18 µs
1.0 s
Current Consumption (Max values)
Continuous Burst Read @ 75 MHz
Program
Erase
Standby Mode
90 mA
50 mA
50 mA
60 µA
Notice for the 32Mb S29CD-J and S29CL-J devices only:
Please refer to the application note “Recommended
Mode of Operation for Spansion
®
110 nm S29CD032J/S29CL032J Flash
Memory”
publication number
S29CD-CL032J_Recommend_AN
for programming best practices.
Cypress Semiconductor Corporation
Document Number: 002-00948 Rev. *A
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 16, 2015
S29CD032J
S29CD016J
S29CL032J
S29CL016J
Contents
1.
1.1
2.
3.
4.
5.
5.1
5.2
5.3
5.4
5.5
5.6
6.
6.1
6.2
6.3
6.4
7.
7.1
8.
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
9.
9.1
9.2
9.3
9.4
9.5
9.6
Ordering Information
................................................... 3
Valid Combinations ........................................................ 4
Input/Output Descriptions and Logic Symbols.........
5
Block Diagram..............................................................
6
Block Diagram of Simultaneous Read/Write Circuit.
7
Physical Dimensions/Connection Diagrams.............
8
80-Pin PQFP Connection Diagram ................................ 8
PQR080–80-Lead Plastic Quad Flat Package Physical Di-
mensions........................................................................ 9
80-Ball Fortified BGA Connection Diagrams................ 10
Special Package Handling Instructions........................ 10
LAA080–80-ball Fortified Ball Grid Array (13 x 11 mm)
Physical Dimensions.................................................... 11
LAD080–80-ball Fortified Ball Grid Array (11 x 9 mm)
Physical Dimensions.................................................... 12
Additional Resources
................................................
Application Notes .........................................................
Specification Bulletins ..................................................
Hardware and Software Support..................................
Contacting Spansion....................................................
13
13
13
13
13
13. Electrical Specifications.............................................
47
13.1 Absolute Maximum Ratings .......................................... 47
14.
Operating Ranges
....................................................... 48
15. DC Characteristics......................................................
48
15.1 Zero Power Flash.......................................................... 49
16.
Test Conditions
........................................................... 50
17. Test Specifications
..................................................... 50
17.1 Switching Waveforms ................................................... 50
18.
18.1
18.2
18.3
18.4
18.5
18.6
18.7
18.8
18.9
AC Characteristics......................................................
51
V
CC
and V
IO
Power-up.................................................. 51
Asynchronous Operations............................................. 52
Synchronous Operations .............................................. 54
Hardware Reset (RESET#)........................................... 56
Write Protect (WP#) ...................................................... 57
Erase/Program Operations ........................................... 57
Alternate CE# Controlled Erase/Program Operations .. 64
Erase and Programming Performance ......................... 66
PQFP and Fortified BGA Pin Capacitance ................... 66
19. Appendix 1
.................................................................. 67
19.1 Common Flash Memory Interface (CFI) ....................... 67
20. Appendix 2
.................................................................. 71
20.1 Command Definitions.................................................... 71
21.
Revision History..........................................................
73
Product Overview
...................................................... 14
Memory Map ................................................................ 14
Device Operations
.....................................................
Device Operation Table ...............................................
Asynchronous Read.....................................................
Hardware Reset (RESET#)..........................................
Synchronous (Burst) Read Mode and Configuration
Register........................................................................
Autoselect ....................................................................
VersatileI/O (V
IO
) Control.............................................
Program/Erase Operations ..........................................
Write Operation Status.................................................
Reset Command ..........................................................
Advanced Sector Protection/Unprotection
.............
Advanced Sector Protection Overview ........................
Persistent Protection Bits.............................................
Persistent Protection Bit Lock Bit.................................
Dynamic Protection Bits...............................................
Password Protection Method .......................................
Hardware Data Protection Methods.............................
19
19
20
20
21
25
26
26
31
37
37
39
39
41
41
42
43
10. Secured Silicon Sector Flash Memory Region
....... 44
10.1 Secured Silicon Sector Protection Bit .......................... 45
10.2 Secured Silicon Sector Entry and Exit Commands...... 45
11.
12.
12.1
12.2
12.3
12.4
Electronic Marking.....................................................
45
Power Conservation Modes......................................
Standby Mode..............................................................
Automatic Sleep Mode.................................................
Hardware RESET# Input Operation.............................
Output Disable (OE#)...................................................
45
45
46
46
46
Document Number: 002-00948 Rev. *A
Page 2 of 86
S29CD032J
S29CD016J
S29CL032J
S29CL016J
1.
Ordering Information
The order number (Valid Combination) is formed by the following:
S29CD032J
S29CL032J
0
J
F
A
I
0
0
0
Packing Type
0 = Tray, FBGA: 180 per tray, min. 10 trays per box
Tray, PQFP: 66 per tray, min. 10 trays per box
2 = 7” Tape and Reel, FBGA: 400 per reel
3 = 13” Tape and Reel, FBGA: 1600 per reel
13” Tape and Reel, PQFP: 500 per reel
Boot Sector Option (16th Character)
0 = Top Boot with Simultaneous Operation
1 = Bottom Boot with Simultaneous Operation
2 = Top Boot without Simultaneous Operation
3 = Bottom Boot without Simultaneous Operation
Autoselect ID Option (15th Character)
0 = 7E, 08, 01/00 Autoselect ID
1 = 7E, 36, 01/00 Autoselect ID
0 = 7E, 46, 01/00 Autoselect ID
0 = 7E, 09, 01/00 Autoselect ID
0 = 7E, 49, 01/00 Autoselect ID
Temperature Range
I = Industrial (–40°C to +85°C)
M = Extended (–40°C to +125°C)
Material Set
A = Standard
F = Pb-free Option
Package Type
Q = Plastic Quad Flat Package (PQFP)
F = Fortified Ball Grid Array, 1.0 mm pitch package, 13 x 11 mm package
B = Fortified Ball Grid Array, 1.0 mm pitch package, 11 x 9 mm package
Clock Frequency (11th Character)
J = 40 MHz
M = 56 MHz
P = 66 MHz
R = 75 MHz
Initial Burst Access Delay (10th Character)
0 = 5-1-1-1, 6-1-1-1, and above
1 = 4-1-1-1 (40 MHz only)
S29CD016J only
S29CL016J only
S29CD032J only
S29CL032J only
Device Number/Description
S29CD032J/S29CD016J (2.5 volt-only), S29CL032J/S29CL016J (3.3 volt-only)
32 or 16 Megabit (1M or 512k x 32-Bit) CMOS Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
Manufactured on 110 nm floating gate technology
Document Number: 002-00948 Rev. *A
Page 3 of 86
S29CD032J
S29CD016J
S29CL032J
S29CL016J
1.1
Valid Combinations
Valid Combinations lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
S29CD-J/CL-J Valid Combinations
Device
Number
Initial Burst
Access Delay
0, 1
S29CD016J
Q
0
M, P
B, F
Q
0, 1
S29CL016J
Q
0
M, P
B, F
Q
0, 1
J
B, F
Q
M, P
B, F
S29CD032J
0
R
B, F
2, 3
Q
0, 1
J
B, F
0, 1, 2, 3
Q
M, P
B, F
S29CL032J
0, 1
(2)
0
R
0, 1
(2)
B, F
2, 3
Notes:
1. The ordering part number that appears on BGA packages omits the leading “S29”.
2. Contact factory for availability.
0, 2, 3
Q
2, 3
0, 3
0, 2, 3
0, 3
0, 2, 3
0, 3
Q
2, 3
0
0, 1
(2)
0, 2, 3
A, F
I, M
0, 1
(2)
0, 3
0, 2, 3
0, 2, 3
0, 3
0, 2, 3
0, 3
J
B, F
0, 1, 2, 3
0, 3
0, 2, 3
0, 2, 3
0, 3
Clock
Frequency
J
B, F
0, 1
0, 3
0, 2, 3
Package
Type
Q
Material
Set
Temperature
Range
Autoselect ID
Option
Boot Sector
Option
Packing
Type
0, 3
Document Number: 002-00948 Rev. *A
Page 4 of 86
S29CD032J
S29CD016J
S29CL032J
S29CL016J
2. Input/Output Descriptions and Logic Symbols
Table identifies the input and output package connections provided on the device.
Symbol
A19-A0
DQ31-DQ0
CE#
OE#
WE#
V
CC
V
IO
V
SS
NC
Type
Input
I/O
Input
Input
Input
Supply
Supply
Supply
No Connect
Description
Address lines for S29CD-J and S29CL-J (A18-A0 for 16 Mb and A19-A0 for 32 Mb).
A9 supports 12V autoselect input.
Data input/output
Chip Enable. This signal is asynchronous relative to CLK for the burst mode.
Output Enable. This signal is asynchronous relative to CLK for the burst mode.
Write Enable
Device Power Supply. This signal is asynchronous relative to CLK for the burst mode.
VersatileI/O
TM
Input.
Ground
Not connected internally
Ready/Busy output and open drain which require a external pull up resistor.
RY/BY#
Output
When RY/BY# = V
OH
, the device is ready to accept read operations and commands.
When RY/BY# = V
OL
, the device is either executing an embedded algorithm or the
device is executing a hardware reset operation.
Clock Input that can be tied to the system or microprocessor clock and provides the
fundamental timing and internal operating frequency.
Load Burst Address input. Indicates that the valid address is present on the address
inputs.
End of burst indicator for finite bursts only. IND is low when the last word in the burst
sequence is at the data outputs.
Provides data valid feedback only when the burst length is set to continuous.
Write Protect Input. At V
IL
, disables program and erase functions in two outermost
sectors of the large bank.
Acceleration input. At V
HH
, accelerates erasing and programming. When not used for
acceleration, ACC = V
SS
or V
CC
.
Hardware Reset.
CLK
ADV#
IND#
WAIT#
WP#
ACC
RESET#
Input
Input
Output
Output
Input
Input
Input
Document Number: 002-00948 Rev. *A
Page 5 of 86
NXP MCU
