S29CD032G Known Good Die
32 Megabit (1 M x 32-Bit) CMOS 2.5 Volt-only
Burst Mode, Dual Boot, Simultaneous Read/Write
Flash Memory
Data Sheet Supplement
This product has been retired and is not recommended for designs. Please contact your Spansion representative for alternates.
Availability of this document is retained for reference and historical purposes only.
Distinctive Characteristics
Architecture Advantages
Simultaneous Read/Write operations
— Data can be continuously read from the 75% bank
while executing erase/program functions in the 25%
bank
— Zero latency between read and write operations
— Two bank architecture: 75%/25%
20 year data retention typical
Versatile I/O™ control
— Device generates data output voltages and tolerates
data input voltages as determined by the voltage on
the V
IO
pin
— 1.65 V to 2.75 V compatible I/O signals
— 3.6 V tolerant I/O signals
User-Defined x32 Data Bus
Dual Boot Block
— Top and bottom boot in the same device
Software Features
Persistent Sector Protection
— A command sector protection method to lock
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector (requires only V
CC
levels)
Flexible sector architecture
— Eight 8 Kbytes, sixty-two 64 Kbytes, and eight 8
Kbytes sectors
Manufactured on 0.17 µm process technology
SecSi (Secured Silicon) Sector (256 Bytes)
—
Factory locked:
SecSi will contain device information
such as manufacturing lot and test information (also
known as Electronic Marking)
Password Sector Protection
— A sophisticated sector protection method to lock
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector using a user-definable 64-bit password
Programmable Burst interface
— Interface to any high performance processor
— Modes of Burst Read Operation:
—
Linear Burst:
4 double words and 8 double words
with wrap around
Supports Common Flash Interface (CFI)
Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
Single power supply operation
— Optimized for 2.5 to 2.75 Volt read, erase, and
program operations
Data# Polling and toggle bits
— Provides a software method of detecting program or
erase operation completion
Compatibility with JEDEC standards (JC42.4)
— Software compatible with single-power supply Flash
— Backward-compatible with Spansion Am29LV and
Am29F, and Fujitsu MBM29LV and MBM29F flash
memories
Hardware Features
Program Suspend/Resume & Erase Suspend/
Resume
— Suspends program or erase operations to allow
reading, programming, or erasing in same bank
Performance Characteristics
High performance read access
— Initial/random access times as fast as 48 ns
— Burst access time as fast as 7.5 ns
Hardware Reset (RESET#), Ready/Busy#
(RY/BY#), and Write Protect (WP#) inputs
ACC input
— Accelerates programming time for higher throughput
during system production
Ultra low power consumption
— Burst Mode Read: 90 mA @ 56 MHz max
— Program/Erase: 50 mA max
— Standby mode: CMOS: 150 µA max
100K write cycles per sector typical
Publication Number
S29CD032G_KGD
Revision
A
Amendment
3
Issue Date
February 23, 2009
S u p p l e m e n t
Table of Contents
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . 3
S29CD032G Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Product Selector Guide. . . . . . . . . . . . . . . . . . . . . . 5
Die Photograph . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Die Pad Location . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pad Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Packaging Information . . . . . . . . . . . . . . . . . . . . . . 9
Surftape Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Waffle Pack Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Product Test Flow . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 11
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Physical Specifications . . . . . . . . . . . . . . . . . . . . . . 12
Manufacturing Information . . . . . . . . . . . . . . . . . . 12
Special Handling Instructions . . . . . . . . . . . . . . . . 12
Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DC characteristics for KGD Devices at 145° C . . . 13
CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Terms and Conditions of Sale for Spansion Non-Vol-
atile Memory Die . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 16
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S29CD032G Known Good Die
S29CD032G_KGDA3 February 23, 2009
S u p p l e m e n t
General Description
The S29CD032G in Known Good Die (KGD) form is a 32 Mbit, 2.5 volt-only Flash
memory. Spansion defines KGD as standard product in die form, tested for func-
tionality and speed.
S29CD032G Features
The S29CD032G is a 32 Megabit, 2.5 Volt-only single power supply burst mode
flash memory device. The device is configured for 1,048,576 double words. The
device can also be programmed in standard EPROM programmers.
To eliminate bus contention, each device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls. Additional control inputs are re-
quired for synchronous burst operations: Load Burst Address Valid (ADV#), and
Clock (CLK).
Each device requires only a
single 2.5 or 2.6 Volt power supply
(2.5 V to 2.75
V) for both read and write functions. A 12.0-volt V
PP
is not required for program
or erase operations, although an acceleration pin is available if faster program-
ming performance is required.
The device is entirely command set compatible with the
JEDEC single-power-
supply Flash standard.
The
Unlock Bypass
mode facilitates faster programming times by requiring only
two write cycles to program data instead of four.
The
Simultaneous Read/Write architecture
provides simultaneous operation
by dividing the memory space into two banks. The device can begin programming
or erasing in the small bank, and then simultaneously read from the large bank,
with zero latency.
The device provides a 256-byte
SecSi™ (Secured Silicon) Sector
that contains
Electronic Marking Information for easy device traceability.
In addition, the device features several levels of sector protection, which can dis-
able both the program and erase operations in certain sectors or sector groups:
Persistent Sector Protection
is a command sector protection method that re-
places the old 12 V controlled protection method;
Password Sector Protection
is a highly sophisticated protection method that requires a password before
changes to certain sectors or sector groups are permitted;
WP# Hardware Pro-
tection
prevents program or erase in the two outermost 8 Kbytes sectors of the
larger bank.
The device defaults to the Persistent Sector Protection mode. The customer must
then choose if the Standard or Password Protection method is most desirable. The
WP# Hardware Protection feature is always available, independent of the other
protection method chosen.
The
Versatile I/O™ (V
CCQ
)
feature allows the output voltage generated on the
device to be determined based on the V
IO
level. This feature allows this device to
operate in the 1.8 V I/O environment, driving and receiving signals to and from
other 1.8 V devices on the same bus. In addition, inputs and I/Os that are driven
externally are capable of handling 3.6 V.
The host system can detect whether a program or erase operation is complete by
observing the RY/BY# pin, by reading the DQ7 (Data# Polling), or DQ6 (toggle)
status bits.
After a program or erase cycle is completed, the device is ready to
read array data or accept another command.
February 23, 2009 S29CD032G_KGD_A3
S29CD032G Known Good Die
3
S u p p l e m e n t
The
sector erase architecture
allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automat-
ically inhibits write operations during power transitions. The
password and
software sector protection
feature disables both program and erase opera-
tions in any combination of sectors of memory. This can be achieved in-system
at V
CC
level.
The
Program/Erase Suspend/Erase Resume
feature enables the user to put
erase on hold for any period of time to read data from, or program data to, any
sector that is not selected for erasure. True background erase can thus be
achieved.
The
hardware RESET# pin
terminates any operation in progress and resets the
internal state machine to reading array data.
The device offers two power-saving features. When addresses are stable for a
specified amount of time, the device enters the
automatic sleep mode.
The
system can also place the device into the
standby mode.
Power consumption is
greatly reduced in both these modes.
Spansion’s Flash technology combines years of Flash memory manufacturing ex-
perience to produce the highest levels of quality, reliability and cost
effectiveness. The device electrically erases all bits within a sector simulta-
neously via Fowler-Nordheim tunneling. The data is programmed using hot
electron injection.
Electrical Specifications
Refer to the S29CD032G data sheet, publication number S29CD-G, for full elec-
trical specifications on the S29CD032G in KGD form.
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S29CD032G Known Good Die
S29CD032G_KGD_A3 February 23, 2009
S u p p l e m e n t
Product Selector Guide
Part Number
Standard Voltage Range: V
CC
= 2.5 – 2.75 V
Speed Option (Clock Rate)
Max Initial/Asynchronous Access Time, ns (t
ACC
)
Max Burst Access Delay (ns)
Max Clock Rate (MHz)
Max CE# Access, ns (t
CE
)
Max OE# Access, ns (t
OE
)
S29CD032G KGD
Synchronous/Burst or Asynchronous
66 MHz
54
9
66
58
20
56 MHz
64
10
56
69
20
40 MHz
67
17
40
71
28
Die Photograph
February 23, 2009 S29CD032G_KGD_A3
S29CD032G Known Good Die
5
电源技术
