S29CD032J
S29CD016J
S29CL032J
S29CL016J
32/16 Mbit, 2.6/3.3 V, Dual Boot,
Simultaneous Read/Write, Burst Flash
General Description
The Cypress S29CD-J and S29CL-J devices are Floating Gate products fabricated in 110-nm process technology. These burst-
mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks,
using separate data and address pins. These products can operate up to 75 MHz (32 Mb) or 66 MHz (16 Mb), and use a single V
CC
of 2.5V to 2.75V (S29CD-J) or 3.0V to 3.6V (S29CL-J) that make them ideal for today’s demanding automotive applications.
Distinctive Characteristics
Single 2.6V (S29CD-J) or 3.3V (S29CL-J) for read/program/
erase
110 nm Floating Gate Technology
Simultaneous Read/Write operation with zero latency
x32 Data Bus
Dual Boot Sector Configuration (top and bottom)
Flexible Sector Architecture
– CD016J and CL016J: Eight 2k Double word, Thirty 16k
Double word, and Eight 2k Double Word sectors
– CD032J and CL032J: Eight 2k Double word, Sixty-two 16k
Double Word, and Eight 2k Double Word sectors
VersatileI/O™ control (1.65V to 3.6V)
Programmable Burst Interface
– Linear for 2, 4, and 8 double word burst with wrap around
Secured Silicon Sector that can be either factory or
customer locked
20 year data retention (typical)
Cycling Endurance: 1 million write cycles per sector (typical)
Command set compatible with JEDEC (JC42.4) standard
Supports Common Flash Interface (CFI)
Extended Temperature range
Persistent and Password methods of Advanced Sector
Protection
Unlock Bypass program command to reduce programming
time
ACC input pin to reduce factory programming time
Data Polling bits indicate program and erase operation
completion
Hardware (WP#) protection of two outermost sectors in the
large bank
Ready/Busy (RY/BY#) output indicates data available to
system
Suspend and Resume commands for Program and Erase
Operation
Offered Packages
– 80-pin PQFP
– 80-ball Fortified BGA (13 x 11 mm and 11 x 9mm versions)
– Pb-free package option available
– Known Good Die
Cypress Semiconductor Corporation
Document Number: 002-00948 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 08, 2017
S29CD032J
S29CD016J
S29CL032J
S29CL016J
Performance Characteristics
Read Access Times
Speed Option (MHz)
Max Asynch. Access Time, ns (t
ACC
)
Max Synch. Burst Access, ns (t
BACC
)
Min Initial Clock Delay (clock cycles)
Max CE# Access Time, ns (t
CE
)
Max OE# Access time, ns (t
OE
)
75 (32 Mb only)
54
8
5
54
20
66
54
8
5
54
20
56
54
8
5
54
20
40
54
8
4
54
20
Current Consumption (Max values)
Continuous Burst Read @ 75 MHz
Program
Erase
Standby Mode
90 mA
50 mA
50 mA
60 µA
Typical Program and Erase Times
Double Word Programming
Sector Erase
18 µs
1.0 s
Notice for the 32Mb S29CD-J and S29CL-J devices only:
Refer to the application note “Recommended
Mode of Operation for Cypress
®
110 nm S29CD032J/S29CL032J Flash Memory”
publication number
S29CD-CL032J_Recommend_AN
for programming best practices.
Document Number: 002-00948 Rev. *C
Page 2 of 74
S29CD032J
S29CD016J
S29CL032J
S29CL016J
Contents
1.
1.1
2.
3.
4.
5.
5.1
5.2
5.3
5.4
5.5
5.6
6.
6.1
7.
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8.
8.1
8.2
8.3
8.4
8.5
8.6
9.
9.1
Ordering Information
................................................... 4
Valid Combinations ........................................................ 5
Input/Output Descriptions
and Logic Symbols
...................................................... 6
Block Diagram..............................................................
7
Block Diagram of Simultaneous
Read/Write Circuit........................................................
8
Physical Dimensions/Connection Diagrams.............
9
80-Pin PQFP Connection Diagram ................................ 9
PQR080–80-Lead Plastic Quad Flat
Package Physical Dimensions..................................... 10
80-Ball Fortified BGA Connection Diagram ................. 11
Special Package Handling Instructions........................ 11
LAA080–80-ball Fortified Ball Grid Array
(13 x 11 mm) Physical Dimensions.............................. 12
LAD080–80-ball Fortified Ball Grid Array
(11 x 9 mm) Physical Dimensions................................ 13
Product Overview
...................................................... 14
Memory Map ................................................................ 14
Device Operations
.....................................................
Device Operation Table ...............................................
Asynchronous Read.....................................................
Hardware Reset (RESET#)..........................................
Synchronous (Burst) Read Mode
and Configuration Register ..........................................
Autoselect ....................................................................
VersatileI/O (V
IO
) Control.............................................
Program/Erase Operations ..........................................
Write Operation Status.................................................
Reset Command ..........................................................
Advanced Sector Protection/Unprotection
.............
Advanced Sector Protection Overview ........................
Persistent Protection Bits.............................................
Persistent Protection Bit Lock Bit.................................
Dynamic Protection Bits...............................................
Password Protection Method .......................................
Hardware Data Protection Methods.............................
19
19
20
21
21
26
27
27
32
36
37
38
39
41
41
42
43
9.2
10.
11.
11.1
11.2
11.3
11.4
Secured Silicon Sector Entry
and Exit Commands...................................................... 45
Electronic Marking......................................................
46
Power Conservation Modes.......................................
46
Standby Mode............................................................... 46
Automatic Sleep Mode.................................................. 46
Hardware RESET# Input Operation.............................. 46
Output Disable (OE#).................................................... 46
12. Electrical Specifications.............................................
47
12.1 Absolute Maximum Ratings .......................................... 47
13.
Operating Ranges
....................................................... 48
14. DC Characteristics......................................................
49
14.1 Zero Power Flash.......................................................... 50
15.
Test Conditions
........................................................... 51
16. Test Specifications
..................................................... 51
16.1 Switching Waveforms ................................................... 51
17.
17.1
17.2
17.3
17.4
17.5
17.6
17.7
AC Characteristics......................................................
52
V
CC
and V
IO
Power-up.................................................. 52
Asynchronous Operations............................................. 52
Synchronous Operations .............................................. 54
Hardware Reset (RESET#)........................................... 56
Write Protect (WP#) ...................................................... 57
Erase/Program Operations ........................................... 57
Alternate CE# Controlled
Erase/Program Operations ........................................... 62
17.8 Erase and Programming Performance ......................... 63
17.9 PQFP and Fortified BGA Pin Capacitance ................... 63
18. Appendix 1
.................................................................. 64
18.1 Common Flash Memory Interface (CFI) ....................... 64
19. Appendix 2
.................................................................. 67
19.1 Command Definitions.................................................... 67
20. Revision History..........................................................
69
Sales, Solutions, and Legal Information .......................... 74
Worldwide Sales and Design Support ........................... 74
Products ........................................................................ 74
PSoC® Solutions .......................................................... 74
Cypress Developer Community ..................................... 74
Technical Support ......................................................... 74
Secured Silicon Sector Flash Memory Region
....... 44
Secured Silicon Sector Protection Bit .......................... 45
Document Number: 002-00948 Rev. *C
Page 3 of 74
S29CD032J
S29CD016J
S29CL032J
S29CL016J
1.
Ordering Information
0
J
F
A
I
0
0
0
Packing Type
0 = Tray, FBGA: 180 per tray, min. 10 trays per box
Tray, PQFP: 66 per tray, min. 10 trays per box
2 = 7” Tape and Reel, FBGA: 400 per reel
3 = 13” Tape and Reel, FBGA: 1600 per reel
13” Tape and Reel, PQFP: 500 per reel
Boot Sector Option (16th Character)
0 = Top Boot with Simultaneous Operation
1 = Bottom Boot with Simultaneous Operation
2 = Top Boot without Simultaneous Operation
3 = Bottom Boot without Simultaneous Operation
Autoselect ID Option (15th Character)
0 = 7E, 08, 01/00 Autoselect ID
1 = 7E, 36, 01/00 Autoselect ID
0 = 7E, 46, 01/00 Autoselect ID
0 = 7E, 09, 01/00 Autoselect ID
0 = 7E, 49, 01/00 Autoselect ID
Temperature Range
I = Industrial (–40 °C to +85 °C)
M = Extended (–40 °C to +125 °C)
Material Set
A = Standard
F = Pb-free Option
Package Type
Q = Plastic Quad Flat Package (PQFP)
F = Fortified Ball Grid Array, 1.0 mm pitch package, 13
11 mm package
B = Fortified Ball Grid Array, 1.0 mm pitch package, 11
9 mm package
Clock Frequency (11th Character)
J = 40 MHz
M = 56 MHz
P = 66 MHz
R = 75 MHz
Initial Burst Access Delay (10th Character)
0 = 5-1-1-1, 6-1-1-1, and above
1 = 4-1-1-1 (40 MHz only)
Device Number/Description
S29CD032J/S29CD016J (2.5 volt-only), S29CL032J/S29CL016J (3.3 Volt-only)
32 or 16 Mbit (1M or 512k
32-Bit) CMOS Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
Manufactured on 110 nm floating gate technology
The order number (Valid Combination) is formed by the following:
S29CD032J
S29CL032J
S29CD016J only
S29CL016J only
S29CD032J only
S29CL032J only
Document Number: 002-00948 Rev. *C
Page 4 of 74
S29CD032J
S29CD016J
S29CL032J
S29CL016J
1.1
Valid Combinations
Valid Combinations lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
S29CD-J/CL-J Valid Combinations
Device
Number
Initial Burst
Access Delay
0, 1
S29CD016J
0
M, P
Clock
Frequency
J
Package
Type
Q
B, F
Q
B, F
Q
B, F
Q
B, F
Q
B, F
Q
B, F
Q
Material
Set
Temperature
Range
Autoselect ID
Option
Boot Sector
Option
Packing
Type
0, 3
0, 2, 3
0, 3
0, 2, 3
0, 3
0, 1
0, 1
S29CL016J
0
J
0, 1, 2, 3
0, 2, 3
0, 3
0, 2, 3
0, 3
0, 2, 3
0, 3
M, P
0, 1
J
M, P
S29CD032J
0
R
A, F
I, M
0, 2, 3
0, 1
(2)
0
2, 3
0, 1
(2)
2, 3
0, 3
B, F
Q
B, F
Q
B, F
Q
R
B, F
0, 2, 3
0, 3
0, 1
J
0, 1, 2, 3
0, 2, 3
0, 3
0, 2, 3
M, P
S29CL032J
0
0, 1
(2)
2, 3
0, 1
(2)
2, 3
0, 3
0, 2, 3
Notes
1. The ordering part number that appears on BGA packages omits the leading “S29”.
2. Contact factory for availability.
Document Number: 002-00948 Rev. *C
Page 5 of 74
DSP 与 ARM 处理器
