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S29GLxxxP MirrorBit

Flash Family

S29GL01GP, S29GL512P, S29GL256P

1 Gigabit, 512 Megabit, and 256 Megabit,

3.0 Volt-only Page Mode Flash Memory featuring

90 nm MirrorBit process technology

Datasheet

ADVANCE

INFORMATION

Distinctive Characteristics

Architectural Advantages

Single power supply operation

— 3 volt read, erase, and program operations

Enhanced VersatileI/O™ control

— All input levels (address, control, and DQ input levels)

and outputs are determined by voltage on V

input.

range is 1.65 to V

Manufactured on 90 nm MirrorBit process

technology

SecSi™ (Secured Silicon) Sector region

— 128-word/256-byte sector for permanent, secure

identification through an 8-word/16-byte random

Electronic Serial Number, accessible through a

command sequence

— Can be programmed and locked at the factory or by

the customer

Flexible sector architecture

— S29GL01GP: One thousand twenty-four 64 Kword

(128 Kbyte) sectors

— S29GL512P: Five hundred twelve 64 Kword

(128 Kbyte) sectors

— S29GL256P: Two hundred fifty-six 64 Kword

(128 Kbyte) sectors

Compatibility with JEDEC standards

— Provides pinout and software compatibility for single-

power supply flash, and superior inadvertent write

protection

100,000 erase cycles per sector typical

20-year data retention typical

Performance Characteristics

High performance

— 100 ns access time (S29GL256P, S29GL512P,

S29GL01GP)

— 8-word/16-byte page read buffer

— 25 ns page read times

— 32-word/64-byte write buffer reduces overall

programming time for multiple-word updates

Low power consumption (typical values at 3.0 V,

5 MHz)

— 25 mA typical active read current;

— 50 mA typical erase/program current

— 1 µA typical standby mode current

Package options

— 56-pin TSOP

— 64-ball Fortified BGA

Software & Hardware Features

Software features

— Program Suspend and Resume: read other sectors

before programming operation is completed

— Erase Suspend and Resume: read/program other

sectors before an erase operation is completed

— Data# polling and toggle bits provide status

— Unlock Bypass Program command reduces overall

multiple-word programming time

— CFI (Common Flash Interface) compliant: allows host

system to identify and accommodate multiple flash

devices

Hardware features

— Advanced Sector Protection

— WP#/ACC input accelerates programming time

(when high voltage is applied) for greater throughput

during system production. Protects first or last sector

regardless of sector protection settings

— Hardware reset input (RESET#) resets device

— Ready/Busy# output (RY/BY#) detects program or

erase cycle completion

Publication Number

S29GLxxxP_00

Revision

Amendment

Issue Date

October 29, 2004

This document contains information on a product under development at Spansion LLC. The information is intended to help you evaluate this product. Spansion LLC

reserves the right to change or discontinue work on this proposed product without notice.

A d v a n c e

I n f o r m a t i o n

General Description

The S29GL01G/512/256P family of devices are 3.0V single power flash memory

manufactured using 90 nm MirrorBit technology. The S29GL01GP is a 1 Gb, or-

ganized as 67,108,864 words or 134,217,728 bytes. The S29GL512P is a 512

Mbit, organized as 33,554,432 words or 67,108,864 bytes. The S29GL256P is a

256 Mbit, organized as 16,777,216 words or 33,554,432 bytes. The devices have

a 16-bit wide data bus that can also function as an 8-bit wide data bus by using

the BYTE# input. The device can be programmed either in the host system or in

standard EPROM programmers.

Access times as fast as 100 ns (S29GL01GP, S29GL512P, S29GL256P) are avail-

able. Note that each access time has a specific operating voltage range (V

) and

an I/O voltage range (V

), as specified in

“Product Selector Guide”

on page 6

and the

“Ordering Information”

on page 12. The devices are offered in a 56-pin

TSOP or 64-ball Fortified BGA package. Each device has separate chip enable

(CE#), write enable (WE#) and output enable (OE#) controls.

Each device requires only a

single 3.0 volt power supply

for both read and

write functions. In addition to a V

input, a high-voltage

accelerated program

(WP#/ACC)

input provides shorter programming times through increased cur-

rent. This feature is intended to facilitate factory throughput during system

production, but can also be used in the field if desired.

The devices are entirely command set compatible with the

JEDEC single-

power-supply Flash standard.

Commands are written to the device using

standard microprocessor write timing. Write cycles also internally latch addresses

and data needed for the programming and erase operations.

The

sector erase architecture

allows memory sectors to be erased and repro-

grammed without affecting the data contents of other sectors. The device is fully

erased when shipped from the factory.

Device programming and erasure are initiated through command sequences.

Once a program or erase operation has begun, the host system need only poll the

DQ7 (Data# Polling) or DQ6 (toggle)

status bits

or monitor the

Ready/Busy#

(RY/BY#)

output to determine whether the operation is complete. To facilitate

programming, an

Unlock Bypass

mode reduces command sequence overhead

by requiring only two write cycles to program data instead of four.

The

Enhanced VersatileI/O™

) control allows the host system to set the volt-

age levels that the device generates and tolerates on all input levels (address, chip

control, and DQ input levels) to the same voltage level that is asserted on the V

pin.

This allows the device to operate in a 1.8 V or 3 V system environment as required.

Hardware data protection

measures include a low V

detector that automat-

ically inhibits write operations during power transitions.

Persistent Sector

Protection

provides in-system, command-enabled protection of any combina-

tion of sectors using a single power supply at V

Password Sector Protection

prevents unauthorized write and erase operations in any combination of sectors

through a user-defined 64-bit password.

The

Erase Suspend/Erase Resume

feature allows the host system to pause an

erase operation in a given sector to read or program any other sector and then

complete the erase operation. The

Program Suspend/Program Resume

fea-

ture enables the host system to pause a program operation in a given sector to

read any other sector and then complete the program operation.

S29GLxxxP MirrorBit

Flash Family

S29GLxxxP_00A0 October 29, 2004

A d v a n c e

I n f o r m a t i o n

The

hardware RESET# pin

terminates any operation in progress and resets the

device, after which it is then ready for a new operation. The RESET# pin can be

tied to the system reset circuitry. A system reset would thus also reset the device,

enabling the host system to read boot-up firmware from the Flash memory

device.

The device reduces power consumption in the

standby mode

when it detects

specific voltage levels on CE# and RESET#, or when addresses have been stable

for a specified period of time.

The

SecSi™ (Secured Silicon) Sector

provides a 128-word/256-byte area for

code or data that can be permanently protected. Once this sector is protected,

no further changes within the sector can occur.

The

Write Protect (WP#/ACC)

feature protects the first or last sector by as-

serting a logic low on the WP# pin.

MirrorBit flash technology combines years of Flash memory manufacturing expe-

rience to produce the highest levels of quality, reliability and cost effectiveness.

The device electrically erases all bits within a sector simultaneously via hot-hole

assisted erase. The data is programmed using hot electron injection.

October 29, 2004 S29GLxxxP_00A0

S29GLxxxP MirrorBit

Flash Family

A d v a n c e

I n f o r m a t i o n

Table of Contents

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .6

S29GL01GP ..............................................................................................................6

S29GL512P ...............................................................................................................6

S29GL256P ..............................................................................................................6

Table 8. Device Geometry Definition .....................................29

Table 9. Primary Vendor-Specific Extended Query ..................30

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 30

Reading Array Data ............................................................................................ 31

Reset Command .................................................................................................. 31

Autoselect Command Sequence ................................................................... 32

Enter SecSi Sector/Exit SecSi Sector Command Sequence ................... 32

Word Program Command Sequence .......................................................... 32

Unlock Bypass Command Sequence .........................................................33

Write Buffer Programming ......................................................................... 34

Accelerated Program .....................................................................................35

Figure 1. Write Buffer Programming Operation....................... 36

Figure 2. Program Operation ............................................... 37

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .8

Special Package Handling Instructions ............................................................9

Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

S29GL01GP ........................................................................................................ 11

S29GL512P .......................................................................................................... 11

S29GL256P ......................................................................................................... 11

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 12

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 13

Table 1. Device Bus Operations ........................................... 13

Program Suspend/Program Resume Command Sequence .....................37

Figure 3. Program Suspend/Program Resume ........................ 38

Word/Byte Configuration .................................................................................13

VersatileIO

) Control ............................................................................. 14

Requirements for Reading Array Data ......................................................... 14

Page Mode Read .............................................................................................. 14

Writing Commands/Command Sequences ................................................. 14

Write Buffer ......................................................................................................15

Accelerated Program Operation ................................................................15

Autoselect Functions ......................................................................................15

Standby Mode ........................................................................................................15

Automatic Sleep Mode ...................................................................................... 16

RESET#: Hardware Reset Pin ......................................................................... 16

Output Disable Mode ........................................................................................ 16

Table 2. Sector Address Table, S29GL01GP, S29GL512P,

S29GL256P ...................................................................... 17

Chip Erase Command Sequence ................................................................... 38

Sector Erase Command Sequence ................................................................ 39

Figure 4. Erase Operation ................................................... 40

Erase Suspend/Erase Resume Commands ..................................................40

Lock Register Command Set Definitions ..................................................... 41

Password Protection Command Set Definitions ....................................... 41

Non-Volatile Sector Protection Command Set Definitions .................. 43

Global Volatile Sector Protection Freeze Command Set ...................... 44

Volatile Sector Protection Command Set .................................................. 44

SecSi Sector Entry Command ......................................................................... 45

SecSi Sector Exit Command ........................................................................... 45

Command Definitions ........................................................................................46

Table 10. S29GL01GP, S29GL512P, S29GL256P Command Defini-

tions, x16 .........................................................................46

Table 11. S29GL01GP, S29GL512P, S29GL256P Command Defini-

tions, x8 ...........................................................................49

Autoselect Mode .................................................................................................17

Table 3. Autoselect Codes, (High Voltage Method) ................. 18

Sector Protection ................................................................................................ 18

Persistent Sector Protection ....................................................................... 18

Password Sector Protection ........................................................................ 18

WP# Hardware Protection ......................................................................... 18

Selecting a Sector Protection Mode ......................................................... 19

Advanced Sector Protection ........................................................................... 19

Lock Register ........................................................................................................ 19

Table 4. Lock Register ........................................................ 20

Write Operation Status ................................................................................... 52

DQ7: Data# Polling ........................................................................................... 52

Figure 5. Data# Polling Algorithm ........................................ 53

RY/BY#: Ready/Busy# ........................................................................................53

DQ6: Toggle Bit I ............................................................................................... 54

Figure 6. Toggle Bit Algorithm ............................................. 55

Persistent Sector Protection .......................................................................... 20

Dynamic Protection Bit (DYB) .................................................................. 20

Persistent Protection Bit (PPB) .................................................................. 21

Persistent Protection Bit Lock (PPB Lock Bit) ..................................... 22

Table 5. Sector Protection Schemes ..................................... 22

DQ2: Toggle Bit II .............................................................................................. 55

Reading Toggle Bits DQ6/DQ2 ..................................................................... 56

DQ5: Exceeded Timing Limits ........................................................................ 56

DQ3: Sector Erase Timer ................................................................................ 57

DQ1: Write-to-Buffer Abort ........................................................................... 57

Table 12. Write Operation Status .........................................58

Figure 7. Maximum Negative Overshoot Waveform................. 59

Figure 8. Maximum Positive

Overshoot Waveform.......................................................... 59

Persistent Protection Mode Lock Bit ...........................................................23

Password Sector Protection ............................................................................23

Password and Password Protection Mode Lock Bit ................................23

64-bit Password .................................................................................................. 24

Persistent Protection Bit Lock (PPB Lock Bit) .......................................... 24

SecSi (Secured Silicon) Sector Flash Memory Region ..............................25

Write Protect (WP#) ....................................................................................... 26

Hardware Data Protection ............................................................................. 26

Low VCC Write Inhibit ................................................................................27

Write Pulse “Glitch” Protection ................................................................27

Logical Inhibit ...................................................................................................27

Power-Up Write Inhibit ................................................................................27

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 59

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 60

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Figure 9. Test Setup........................................................... 61

Table 13. Test Specifications ...............................................61

Key to Switching Waveforms . . . . . . . . . . . . . . . . 61

Figure 10. Input Waveforms and

Measurement Levels........................................................... 61

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 62

Read-Only Operations-S29GL01GP, S29GL512P, S29GL256P .............. 62

Common Flash Memory Interface (CFI) . . . . . . 27

Table 6. CFI Query Identification String ................................ 28

Table 7. System Interface String ......................................... 28

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 11. Read Operation Timings....................................... 63

Figure 12. Page Read Timings.............................................. 63

Hardware Reset (RESET#) .............................................................................. 64

S29GLxxxP MirrorBit

Flash Family

S29GLxxxP_00A0 October 29, 2004

A d v a n c e

I n f o r m a t i o n

Figure 13. Reset Timings..................................................... 64

Erase and Program Operations-S29GL01GP, S29GL512P, S29GL256P 65

Figure 14. Program Operation Timings .................................. 66

Figure 15. Accelerated Program Timing Diagram .................... 66

Figure 16. Chip/Sector Erase Operation Timings ..................... 67

Figure 17. Data# Polling Timings (During Embedded Algorithms) .

Figure 18. Toggle Bit Timings (During Embedded Algorithms) .. 69

Figure 19. DQ2 vs. DQ6. ..................................................... 69

Figure 20. Alternate CE# Controlled Write (Erase/Program)

Operation Timings.............................................................. 71

Erase And Programming Performance . . . . . . . . 72

TSOP Pin and BGA Package Capacitance . . . . . 72

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 73

TS056—56-Pin Standard Thin Small Outline Package (TSOP) ..............73

LAA064—64-Ball Fortified Ball Grid Array (FBGA) ............................... 74

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 75

Alternate CE# Controlled Erase and Program Operations-S29GL01GP,

S29GL512P, S29GL256N ................................................................................... 70

October 29, 2004 S29GLxxxP_00A0

S29GLxxxP MirrorBit

Flash Family