S29GL01GS/S29GL512S
S29GL256S/S29GL128S
1-Gbit (128 Mbyte)/512-Mbit (64 Mbyte)/
256-Mbit (32 Mbyte)/128-Mbit (16 Mbyte),
3.0 V, GL-S Flash Memory
General Description
The Cypress
®
S29GL01G/512/256/128S are MirrorBit
®
Eclipse flash products fabricated on 65 nm process technology. These
devices offer a fast page access time as fast as 15 ns with a corresponding random access time as fast as 90 ns. They feature a
Write Buffer that allows a maximum of 256 words/512 bytes to be programmed in one operation, resulting in faster effective
programming time than standard programming algorithms. This makes these devices ideal for today’s embedded applications that
require higher density, better performance and lower power consumption.
Distinctive Characteristics
CMOS 3.0 Volt Core with Versatile I/O
65 nm MirrorBit Eclipse Technology
Single supply (V
CC
) for read / program / erase (2.7V to 3.6V)
Versatile I/O Feature
– Wide I/O voltage range (V
IO
): 1.65V to V
CC
x16 data bus
Asynchronous 32-byte Page read
512-byte Programming Buffer
– Programming in Page multiples, up to a maximum of 512
bytes
Single word and multiple program on same word options
Automatic Error Checking and Correction (ECC) – internal
hardware ECC with single bit error correction
Sector Erase
– Uniform 128-kbyte sectors
Suspend and Resume commands for Program and Erase
operations
Status Register, Data Polling, and Ready/Busy pin methods
to determine device status
Advanced Sector Protection (ASP)
– Volatile and non-volatile protection methods for each
sector
Separate 1024-byte One Time Program (OTP) array with two
lockable regions
Common Flash Interface (CFI) parameter table
Temperature Range / Grade
– Industrial (-40°C to +85°C)
– Industrial Plus(-40°C to +105°C)
– Automotive, AEC-Q100 Grade 3 (-40 °C to +85 °C)
– Automotive, AEC-Q100 Grade 2 (-40 °C to +105 °C)
100,000 Program / Erase Cycles
20 Years Data Retention
Packaging Options
– 56-pin TSOP
– 64-ball LAA Fortified BGA, 13 mm × 11 mm
– 64-ball LAE Fortified BGA, 9 mm × 9 mm
– 56-ball VBU Fortified BGA, 9 mm × 7 mm
Cypress Semiconductor Corporation
Document Number: 001-98285 Rev. *P
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 30, 2018
S29GL01GS/S29GL512S
S29GL256S/S29GL128S
Performance Summary
Maximum Read Access Times
Density
128 Mb
256 Mb
512 Mb
1 Gb
Voltage Range
Full V
CC
= V
IO
VersatileIO V
IO
Full V
CC
= V
IO
VersatileIO V
IO
Full V
CC
= V
IO
VersatileIO V
IO
Full V
CC
= V
IO
VersatileIO V
IO
Random Access
Time (t
ACC
)
90
100
90
100
100
110
100
110
Page Access Time
(t
PACC
)
15
25
15
25
15
25
15
25
CE# Access Time
(t
CE
)
90
100
90
100
100
110
100
110
OE# Access Time
(t
OE
)
25
35
25
35
25
35
25
35
Typical Program and Erase Rates
Buffer Programming
(512 bytes)
Sector Erase (128 kbytes)
1.5 MB/s
477 kB/s
Maximum Current Consumption
Active Read at 5 MHz, 30 pF
Program
Erase
Standby
60 mA
100 mA
100 mA
100 µA
Document Number: 001-98285 Rev. *P
Page 3 of 108
S29GL01GS/S29GL512S
S29GL256S/S29GL128S
Contents
General Description
............................................................. 2
Distinctive Characteristics
.................................................. 2
Performance Summary
........................................................ 3
1.
2.
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
3.
3.1
3.2
3.3
3.4
4.
4.1
4.2
5.
5.1
5.2
5.3
5.4
5.5
5.6
5.7
6.
6.1
6.2
7.
7.1
7.2
7.3
8.
8.1
8.2
8.3
8.4
8.5
9.
9.1
9.2
9.3
Product Overview
........................................................ 4
Address Space Maps
................................................... 6
Flash Memory Array....................................................... 7
Device ID and CFI (ID-CFI) ASO ................................... 8
Device ID and Common Flash Interface (ID-CFI) ASO Map
— Automotive Only ........................................................ 9
Status Register ASO.................................................... 10
Data Polling Status ASO.............................................. 10
Secure Silicon Region ASO ......................................... 10
Sector Protection Control............................................. 11
ECC Status ASO.......................................................... 11
Data Protection
..........................................................
Device Protection Methods ..........................................
Command Protection ...................................................
Secure Silicon Region (OTP).......................................
Sector Protection Methods...........................................
13
13
13
13
14
9.4
9.5
10.
10.1
10.2
10.3
10.4
10.5
10.6
11.
11.1
11.2
11.3
11.4
12.
12.1
12.2
12.3
13.
14.
15.
15.1
15.2
15.3
16.
Read ............................................................................. 67
Write ............................................................................. 68
Electrical Specifications.............................................
69
Absolute Maximum Ratings .......................................... 69
Latchup Characteristics ................................................ 69
Thermal Resistance ...................................................... 69
Operating Ranges......................................................... 69
DC Characteristics ........................................................ 72
Capacitance Characteristics ......................................... 74
Timing Specifications.................................................
75
Key to Switching Waveforms ........................................ 75
AC Test Conditions ....................................................... 75
Power-On Reset (POR) and Warm Reset .................... 76
AC Characteristics ........................................................ 78
Physical Interface
....................................................... 90
56-Pin TSOP................................................................. 90
64-Ball FBGA ................................................................ 92
56-Ball FBGA ................................................................ 95
Special Handling Instructions for FBGA Package...
96
Ordering Information
.................................................. 97
Other Resources
....................................................... 102
Cypress Flash Memory Roadmap .............................. 102
Links to Software ........................................................ 102
Links to Application Notes........................................... 102
Revision History........................................................
103
Read Operations
........................................................ 19
Asynchronous Read..................................................... 19
Page Mode Read ......................................................... 19
Embedded Operations...............................................
Embedded Algorithm Controller (EAC) ........................
Program and Erase Summary .....................................
Automatic ECC ............................................................
Command Set ..............................................................
Status Monitoring .........................................................
Error Types and Clearing Procedures .........................
Embedded Algorithm Performance Table....................
20
20
21
22
23
34
40
43
Data Integrity
.............................................................. 54
Erase Endurance ......................................................... 54
Data Retention ............................................................. 54
Software Interface Reference
...................................
Command Summary ....................................................
Device ID and Common Flash Interface (ID-CFI)
ASO Map .....................................................................
Device ID and Common Flash Interface (ID-CFI)
ASO Map .....................................................................
Signal Descriptions
...................................................
Address and Data Configuration..................................
Input/Output Summary.................................................
Versatile I/O Feature....................................................
Ready/Busy# (RY/BY#) ...............................................
Hardware Reset ...........................................................
Signal Protocols.........................................................
Interface States............................................................
Power-Off with Hardware Data Protection ...................
Power Conservation Modes.........................................
55
55
58
63
64
64
64
65
65
65
66
66
66
67
Document Number: 001-98285 Rev. *P
Page 3 of 108
S29GL01GS/S29GL512S
S29GL256S/S29GL128S
1.
Product Overview
The GL-S family consists of 128-Mbit to 1Gbit, 3.0V core, Versatile I/O, non-volatile, flash memory devices. These devices have a
16-bit (word) wide data bus and use only word boundary addresses. All read accesses provide 16 bits of data on each bus transfer
cycle. All writes take 16 bits of data from each bus transfer cycle.
Figure 1.1
Block Diagram
RY/BY#
DQ15
–
DQ0
Sector Switches
V
CC
V
SS
V
IO
RESET#
Erase Voltage
Generator
Input/Output
Buffers
WE#
WP#
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data
Latch
CE#
OE#
Y-Decoder
STB
Y-Gating
Address Latch
V
CC
Detector
Timer
X-Decoder
Cell Matrix
A
Max
**–A0
:
Note:
** A
MAX
GL01GS = A25, A
MAX
GL512S = A24, A
MAX
GL256S = A23, A
MAX
GL128S = A22
The GL-S family combines the best features of eXecute In Place (XIP) and Data Storage flash memories. This family has the fast
random access of XIP flash along with the high density and fast program speed of Data Storage flash.
Read access to any random location takes 90 ns to 120 ns depending on device density and I/O power supply voltage. Each random
(initial) access reads an entire 32-byte aligned group of data called a Page. Other words within the same Page may be read by
changing only the low order 4 bits of word address. Each access within the same Page takes 15 ns to 30 ns. This is called Page
Mode read. Changing any of the higher word address bits will select a different Page and begin a new initial access. All read
accesses are asynchronous.
Document Number: 001-98285 Rev. *P
Page 4 of 108
S29GL01GS/S29GL512S
S29GL256S/S29GL128S
Table 1.1
S29GL-S Address Map
Type
Address within Page
Address within Write Buffer
Page
Write-Buffer-Line
Count
16
256
4096
256
1024 (1 Gb)
512 (512 Mb)
256 (256 Mb)
128 (128 Mb)
Addresses
A3 - A0
A7 - A0
A15 - A4
A15 - A8
Sector
A
MAX
- A16
The device control logic is subdivided into two parallel operating sections, the Host Interface Controller (HIC) and the Embedded
Algorithm Controller (EAC). HIC monitors signal levels on the device inputs and drives outputs as needed to complete read and write
data transfers with the host system. HIC delivers data from the currently entered address map on read transfers; places write
transfer address and data information into the EAC command memory; notifies the EAC of power transition, hardware reset, and
write transfers. The EAC looks in the command memory, after a write transfer, for legal command sequences and performs the
related Embedded Algorithms.
Changing the non-volatile data in the memory array requires a complex sequence of operations that are called Embedded
Algorithms (EA). The algorithms are managed entirely by the device internal EAC. The main algorithms perform programming and
erase of the main array data. The host system writes command codes to the flash device address space. The EAC receives the
commands, performs all the necessary steps to complete the command, and provides status information during the progress of an
EA.
The erased state of each memory bit is a logic 1. Programming changes a logic 1 (High) to a logic 0 (Low). Only an Erase operation
is able to change a 0 to a 1. An erase operation must be performed on an entire 128-kbyte aligned and length group of data call a
Sector. When shipped from Cypress all Sectors are erased.
Programming is done via a 512-byte Write Buffer. It is possible to write from 1 to 256 words, anywhere within the Write Buffer before
starting a programming operation. Within the flash memory array, each 512-byte aligned group of 512 bytes is called a Line. A
programming operation transfers volatile data from the Write Buffer to a non-volatile memory array Line. The operation is called
Write Buffer Programming.
As the device transfers each 32-byte aligned page of data that was loaded into the Write buffer to the 512-byte Flash array line,
internal logic programs an ECC Code for the Page into a portion of the memory array not visible to the host system software. The
internal logic checks the ECC information during the initial access of every array read operation. If needed, the ECC information
corrects a one bit error during the initial access time.
The Write Buffer is filled with 1’s after reset or the completion of any operation using the Write Buffer. Any locations not written to a 0
by a Write to Buffer command are by default still filled with 1’s. Any 1’s in the Write Buffer do not affect data in the memory array
during a programming operation.
As each Page of data that was loaded into the Write Buffer is transferred to a memory array Line.
Sectors may be individually protected from program and erase operations by the Advanced Sector Protection (ASP) feature set.
ASP provides several, hardware and software controlled, volatile and non-volatile, methods to select which sectors are protected
from program and erase operations.
Document Number: 001-98285 Rev. *P
Page 5 of 108
