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S29JL064H

64 Megabit (8 M x 8-Bit/4 M x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Read/Write

Flash Memory

Distinctive Characteristics

Architectural Advantages

Simultaneous Read/Write operations

— Data can be continuously read from one bank while

executing erase/program functions in another bank.

— Zero latency between read and write operations

Flexible Bank architecture

— Read may occur in any of the three banks not being

written or erased.

— Four banks may be grouped by customer to achieve

desired bank divisions.

Boot Sectors

— Top and bottom boot sectors in the same device

— Any combination of sectors can be erased

Manufactured on 0.13 µm process technology

SecSi™ (Secured Silicon) Sector: Extra 256 Byte

sector

—

Factory locked and identifiable:

16 bytes available for

secure, random factory Electronic Serial Number;

verifiable as factory locked through autoselect

function.

—

Customer lockable:

One-time programmable only.

Once locked, data cannot be changed

Zero Power Operation

— Sophisticated power management circuits reduce

power consumed during inactive periods to nearly

zero.

Compatible with JEDEC standards

— Pinout and software compatible with single-power-

supply flash standard

Ultra low power consumption (typical values)

— 2 mA active read current at 1 MHz

— 10 mA active read current at 5 MHz

— 200 nA in standby or automatic sleep mode

Cycling Endurance: 1 million cycles per sector

typical

Data Retention: 20 years typical

PRELIMINARY

Software Features

Supports Common Flash Memory Interface (CFI)

Erase Suspend/Erase Resume

— Suspends erase operations to read data from, or

program data to, a sector that is not being erased,

then resumes the erase operation.

Data# Polling and Toggle Bits

— Provides a software method of detecting the status of

program or erase cycles

Unlock Bypass Program command

— Reduces overall programming time when issuing

multiple program command sequences

Hardware Features

Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or erase

cycle completion

Hardware reset pin (RESET#)

— Hardware method of resetting the internal state

machine to the read mode

WP#/ACC input pin

— Write protect (WP#) function protects sectors 0, 1,

140, and 141, regardless of sector protect status

— Acceleration (ACC) function accelerates program

timing

Sector protection

— Hardware method to prevent any program or erase

operation within a sector

— Temporary Sector Unprotect allows changing data in

protected sectors in-system

Package options

63-ball Fine Pitch BGA

48-pin TSOP

Performance Characteristics

High performance

— Access time as fast as 55 ns

— Program time: 4 µs/word typical using accelerated

programming function

Publication Number

S29JL064H

Revision

Amendment

Issue Date

March 26, 2004

This document contains information on a product under development at FASL LLC. The information is intended to help you evaluate this product. FASL LLC reserves the

right to change or discontinue work on this proposed product without notice.

P r e l i m i n a r y

General Description

The S29JL064H is a 64 megabit, 3.0 volt-only flash memory device, organized as

4,194,304 words of 16 bits each or 8,388,608 bytes of 8 bits each. Word mode

data appears on DQ15–DQ0; byte mode data appears on DQ7–DQ0. The device

is designed to be programmed in-system with the standard 3.0 volt V

supply,

and can also be programmed in standard EPROM programmers.

The device is available with an access time of 55, 60, 70, or 90 ns and is offered

in 48-pin TSOP and 63-ball Fine Pitch BGA packages. Standard control pins—chip

enable (CE#), write enable (WE#), and output enable (OE#)—control normal

read and write operations, and avoid bus contention issues.

The device requires only a

single 3.0 volt power supply

for both read and write

functions. Internally generated and regulated voltages are provided for the pro-

gram and erase operations.

Simultaneous Read/Write Operations with Zero Latency

The Simultaneous Read/Write architecture provides

simultaneous operation

by dividing the memory space into

four banks,

two 8 Mb banks with small and

large sectors, and two 24 Mb banks of large sectors. Sector addresses are fixed,

system software can be used to form user-defined bank groups.

During an Erase/Program operation, any of the three non-busy banks may be

read from. Note that only two banks can operate simultaneously. The device can

improve overall system performance by allowing a host system to program or

erase in one bank, then immediately and simultaneously read from the other

bank, with zero latency. This releases the system from waiting for the completion

of program or erase operations.

The S29JL064H can be organized as both a top and bottom boot sector

configuration.

Bank

Bank 1

Bank 2

Bank 3

Bank 4

Megabits

8 Mb

24 Mb

8 Mb

Sector Sizes

Eight 8 Kbyte/4 Kword,

Fifteen 64 Kbyte/32 Kword

Forty-eight 64 Kbyte/32 Kword

Eight 8 Kbyte/4 Kword,

Fifteen 64 Kbyte/32 Kword

S29JL064H Features

The

SecSi™ (Secured Silicon) Sector

is an extra 256 byte sector capable of

being permanently locked by FASL or customers. The SecSi Customer Indicator

Bit (DQ6) is permanently set to 1 if the part has been customer locked, perma-

nently set to 0 if the part has been factory locked, and is 0 if customer lockable.

This way, customer lockable parts can never be used to replace a factory locked

part.

Factory locked parts provide several options. The SecSi Sector may store a se-

cure, random 16 byte ESN (Electronic Serial Number), customer code

(programmed through Spansion programming services), or both. Customer Lock-

able parts may utilize the SecSi Sector as bonus space, reading and writing like

any other flash sector, or may permanently lock their own code there.

S29JL064H

S29JL064HA1 March 26, 2004

P r e l i m i n a r y

DMS (Data Management Software)

allows systems to easily take advantage

of the advanced architecture of the simultaneous read/write product line by al-

lowing removal of EEPROM devices. DMS will also allow the system software to

be simplified, as it will perform all functions necessary to modify data in file struc-

tures, as opposed to single-byte modifications. To write or update a particular

piece of data (a phone number or configuration data, for example), the user only

needs to state which piece of data is to be updated, and where the updated data

is located in the system. This is an advantage compared to systems where user-

written software must keep track of the old data location, status, logical to phys-

ical translation of the data onto the Flash memory device (or memory devices),

and more. Using DMS, user-written software does not need to interface with the

Flash memory directly. Instead, the user's software accesses the Flash memory

by calling one of only six functions.

The device offers complete compatibility with the

JEDEC 42.4 sin-

gle-power-supply Flash command set standard.

Commands are written to

the command register using standard microprocessor write timings. Reading data

out of the device is similar to reading from other Flash or EPROM devices.

The host system can detect whether a program or erase operation is complete by

using the device

status bits:

RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2

(toggle bits). After a program or erase cycle has been completed, the device au-

tomatically returns to the read mode.

The

sector erase architecture

allows memory sectors to be erased and repro-

grammed without affecting the data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection

measures include a low V

detector that automat-

ically inhibits write operations during power transitions. The

hardware sector

protection

feature disables both program and erase operations in any combina-

tion of the sectors of memory. This can be achieved in-system or via

programming equipment.

The device offers two power-saving features. When addresses have been stable

for a specified amount of time, the device enters the

automatic sleep mode.

The system can also place the device into the

standby mode.

Power consump-

tion is greatly reduced in both modes.

March 26, 2004 S29JL064HA1

S29JL064H

P r e l i m i n a r y

Table Of Contents

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .5

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .6

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 10

Table 1. S29JL064H Device Bus Operations ..........................10

DQ6: Toggle Bit I ..................................................................................40

Figure 7. Toggle Bit Algorithm ............................................ 41

DQ2: Toggle Bit II ................................................................................. 41

Reading Toggle Bits DQ6/DQ2 ........................................................ 42

DQ5: Exceeded Timing Limits .......................................................... 42

DQ3: Sector Erase Timer .................................................................. 42

Table 9. Write Operation Status ......................................... 43

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 44

Figure 8. Maximum Negative Overshoot Waveform................ 44

Figure 9. Maximum Positive Overshoot Waveform ................. 44

Requirements for Reading Array Data ............................................ 11

Writing Commands/Command Sequences .................................... 11

Accelerated Program Operation ...................................................... 12

Autoselect Functions ............................................................................ 12

Simultaneous Read/Write Operations with Zero Latency ....... 12

Automatic Sleep Mode ......................................................................... 13

RESET#: Hardware Reset Pin ............................................................ 13

Output Disable Mode ........................................................................... 14

Table 2. S29JL064H Sector Architecture ...............................15

Table 3. Bank Address .......................................................18

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . .44

Industrial (I) Devices ............................................................................ 44

Extended (N) Devices ......................................................................... 44

Supply Voltages ............................................................................ 44

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 45

CMOS Compatible ............................................................................... 45

Figure 10. I

CC1

Current vs. Time (Showing Active and

Automatic Sleep Currents) ................................................. 46

Figure 11. Typical I

CC1

vs. Frequency .................................. 46

Autoselect Mode ...................................................................................18

Table 5. S29JL064H Autoselect Codes, (High Voltage

Method) .........................................................................19

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 12. Test Setup ....................................................... 47

Sector/Sector Block Protection and Unprotection .................... 19

Table 6. S29JL064H Boot Sector/Sector Block Addresses for

Protection/Unprotection .....................................................20

Key To Switching Waveforms . . . . . . . . . . . . . . . . 47

Figure 13. Input Waveforms and Measurement Levels............ 47

Write Protect (WP#) ........................................................................... 21

Table 7. WP#/ACC Modes ..................................................21

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 48

Read-Only Operations ......................................................................48

Figure 14. Read Operation Timings...................................... 48

Temporary Sector Unprotect ........................................................... 21

Figure 1. Temporary Sector Unprotect Operation................... 22

Figure 2. In-System Sector Protect/Unprotect Algorithms ....... 23

Hardware Reset (RESET#) ................................................................ 49

Figure 15. Reset Timings ................................................... 49

Word/Byte Configuration (BYTE#) ................................................ 50

Figure 16. BYTE# Timings for Read Operations ..................... 51

Figure 17. BYTE# Timings for Write Operations..................... 51

SecSi™ (Secured Silicon) Sector

Flash Memory Region .......................................................................... 24

Figure 3. SecSi Sector Protect Verify ................................... 25

Erase and Program Operations ........................................................ 52

Figure 18. Program Operation Timings ................................. 53

Figure 19. Accelerated Program Timing Diagram ................... 53

Figure 20. Chip/Sector Erase Operation Timings.................... 54

Figure 21. Back-to-back Read/Write Cycle Timings ................ 55

Figure 22. Data# Polling Timings (During Embedded

Algorithms)...................................................................... 55

Figure 23. Toggle Bit Timings (During Embedded

Algorithms)...................................................................... 56

Figure 24. DQ2 vs. DQ6 ..................................................... 56

Hardware Data Protection ................................................................ 25

Low VCC Write Inhibit ...................................................................... 25

Write Pulse “Glitch” Protection ...................................................... 26

Logical Inhibit ......................................................................................... 26

Power-Up Write Inhibit ..................................................................... 26

Common Flash Memory Interface (CFI) . . . . . . .26

Command Definitions . . . . . . . . . . . . . . . . . . . . . .30

Reading Array Data ............................................................................. 30

Reset Command ................................................................................... 30

Autoselect Command Sequence ....................................................... 31

Enter SecSi™ Sector/Exit SecSi Sector

Command Sequence ............................................................................. 31

Byte/Word Program Command Sequence .................................... 31

Unlock Bypass Command Sequence ............................................... 32

Figure 4. Program Operation .............................................. 33

Temporary Sector Unprotect .......................................................... 57

Figure 25. Temporary Sector Unprotect Timing Diagram......... 57

Figure 26. Sector/Sector Block Protect and

Unprotect Timing Diagram ................................................. 58

Alternate CE# Controlled Erase and Program Operations .... 59

Figure 27. Alternate CE# Controlled Write (Erase/Program)

Operation Timings............................................................. 60

Chip Erase Command Sequence .......................................................33

Sector Erase Command Sequence .................................................. 34

Figure 5. Erase Operation .................................................. 35

Erase Suspend/Erase Resume Commands .....................................35

Write Operation Status . . . . . . . . . . . . . . . . . . . . .38

DQ7: Data# Polling .............................................................................. 38

Figure 6. Data# Polling Algorithm ....................................... 39

Erase And Programming Performance . . . . . . . . 61

TSOP & BGA Pin Capacitance . . . . . . . . . . . . . . 61

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 62

FBE063—63-Ball Fine-Pitch Ball Grid Array (BGA)

12 x 11 mm package ............................................................................... 62

TS 048—48-Pin Standard TSOP ...................................................... 63

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 64

S29JL064H

S29JL064HA1 March 26, 2004

P r e l i m i n a r y

Product Selector Guide

Part Number

Speed Option

Standard Voltage Range: V

= 2.7–3.6 V

S29JL064H

Max Access Time (ns), t

ACC

CE# Access (ns), t

OE# Access (ns), t

Block Diagram

OE#

BYTE#

Mux

A21–A0

Bank 1 Address

Bank 1

Y-gate

X-Decoder

A21–A0

RY/BY#

Bank 2 Address

Bank 2

X-Decoder

A21–A0

RESET#

WE#

CE#

BYTE#

WP#/ACC

DQ0–DQ15

STATE

CONTROL

COMMAND

Status

DQ15–DQ0

Control

Mux

A21–A0

X-Decoder

Bank 3 Address

Bank 3

DQ15–DQ0

Y-gate

X-Decoder

A21–A0

Mux

Bank 4 Address

Bank 4

March 26, 2004 S29JL064HA1

S29JL064H