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S29PL-J

128/128/64/32 Megabit (8/8/4/2 M x 16-Bit)

CMOS 3.0-Volt only, Simultaneous Read/Write

Flash Memory with Enhanced VersatileIO

Control

Data Sheet

ADVANCE

INFORMATION

Notice to Readers:

This document states the current technical specifications

regarding the Spansion product(s) described herein. Each product described

herein may be designated as Advance Information, Preliminary, or Full

Production. See the section

Notice On Data Sheet Designations

for definitions.

Publication Number

S29PL-J_00

Revision

Amendment

Issue Date

July 29, 2005

This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not

design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.

A d v a n c e

I n f o r m a t i o n

Notice On Data Sheet Designations

Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise

readers of product information or intended specifications throughout the product life cycle, in-

cluding development, qualification, initial production, and full production. In all cases, however,

readers are encouraged to verify that they have the latest information before finalizing their de-

sign. The following descriptions of Spansion data sheet designations are presented here to

highlight their presence and definitions.

Advance Information

The Advance Information designation indicates that Spansion LLC is developing one or more spe-

cific products, but has not committed any design to production. Information presented in a

document with this designation is likely to change, and in some cases, development on the prod-

uct may discontinue. Spansion LLC therefore places the following conditions upon Advance

Information content:

“This document contains information on one or more products under development at Spansion LLC. The

information is intended to help you evaluate this product. Do not design in this product without con-

tacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed

product without notice.”

Preliminary

The Preliminary designation indicates that the product development has progressed such that a

commitment to production has taken place. This designation covers several aspects of the prod-

uct life cycle, including product qualification, initial production, and the subsequent phases in the

manufacturing process that occur before full production is achieved. Changes to the technical

specifications presented in a Preliminary document should be expected while keeping these as-

pects of production under consideration. Spansion places the following conditions upon

Preliminary content:

“This document states the current technical specifications regarding the Spansion product(s) described

herein. The Preliminary status of this document indicates that product qualification has been completed,

and that initial production has begun. Due to the phases of the manufacturing process that require

maintaining efficiency and quality, this document may be revised by subsequent versions or modifica-

tions due to changes in technical specifications.”

Combination

Some data sheets will contain a combination of products with different designations (Advance

Information, Preliminary, or Full Production). This type of document will distinguish these prod-

ucts and their designations wherever necessary, typically on the first page, the ordering

information page, and pages with DC Characteristics table and AC Erase and Program table (in

the table notes). The disclaimer on the first page refers the reader to the notice on this page.

Full Production (No Designation on Document)

When a product has been in production for a period of time such that no changes or only nominal

changes are expected, the Preliminary designation is removed from the data sheet. Nominal

changes may include those affecting the number of ordering part numbers available, such as the

addition or deletion of a speed option, temperature range, package type, or V

range. Changes

may also include those needed to clarify a description or to correct a typographical error or in-

correct specification. Spansion LLC applies the following conditions to documents in this

category:

“This document states the current technical specifications regarding the Spansion product(s) described

herein. Spansion LLC deems the products to have been in sufficient production volume such that sub-

sequent versions of this document are not expected to change. However, typographical or specification

corrections, or modifications to the valid combinations offered may occur.”

Questions regarding these document designations may be directed to your local AMD or Fujitsu

sales office.

S29PL-J

S29PL-J_00_A8 July 29, 2005

S29PL-J

128/128/64/32 Megabit (8/8/4/2 M x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous-Read/Write

Flash Memory with Enhanced VersatileIO™ Control

Data Sheet

ADVANCE

INFORMATION

Distinctive Characteristics

Architectural Advantages

128/128/64/32 Mbit Page Mode devices

—

Page size of 8 words: Fast page read access from random

locations within the page

Full Voltage range: 2.7 to 3.6 volt read, erase, and program

operations for battery-powered applications

Two CE# inputs control selection of each half of the memory

space

Data can be continuously read from one bank while executing

erase/program functions in another bank

Zero latency switching from write to read operations

4 separate banks, with up to two simultaneous operations per

device

Bank A:

PL127J -16 Mbit (4 Kw x 8 and 32 Kw x 31)

PL064J - 8 Mbit (4 Kw x 8 and 32 Kw x 15)

PL032J - 4 Mbit (4 Kw x 8 and 32 Kw x 7)

Bank B:

PL127J - 48 Mbit (32 Kw x 96)

PL064J - 24 Mbit (32 Kw x 48)

PL032J - 12 Mbit (32 Kw x 24)

Bank C:

PL127J - 48 Mbit (32 Kw x 96)

PL064J - 24 Mbit (32 Kw x 48)

PL032J - 12 Mbit (32 Kw x 24)

Bank D:

PL127J -16 Mbit (4 Kw x 8 and 32 Kw x 31)

PL064J - 8 Mbit (4 Kw x 8 and 32 Kw x 15)

PL032J - 4 Mbit (4 Kw x 8 and 32 Kw x 7)

4 separate banks, with up to two simultaneous operations per

device

CE#1 controlled banks:

Bank 1A: PL129J - 16Mbit (4Kw x 8 and 32Kw x 31)

Bank 1B: PL129J - 48Mbit (32Kw x 96)

CE#2 controlled banks:

Bank 2A: PL129J - 48 Mbit (32Kw x 96)

Bank 2B: PL129J - 16Mbit (4Kw x 8 and 32Kw x 31)

Output voltage generated and input voltages tolerated on all

control inputs and I/Os is determined by the voltage on the

options at 1.8 V and 3 V I/O for PL127J and PL129J

devices

3V V

for PL064J and PL032J devices

Up to 128 words accessible through a command sequence

Up to 64 factory-locked words

Up to 64 customer-lockable words

Performance Characteristics

High Performance

—

Page access times as fast as 20 ns

Random access times as fast as 55 ns

45 mA active read current

17 mA program/erase current

0.2 µA typical standby mode current

Single power supply operation

—

Power consumption (typical values at 10 MHz)

Dual Chip Enable inputs (only in PL129J)

—

Software Features

Software command-set compatible with JEDEC 42.4

standard

—

Backward compatible with Am29F, Am29LV, Am29DL, and

AM29PDL families and MBM29QM/RM, MBM29LV, MBM29DL,

MBM29PDL families

Provides device-specific information to the system, allowing

host software to easily reconfigure for different Flash devices

Suspends an erase operation to allow read or program

operations in other sectors of same bank

Suspends a program operation to allow read operation from

sectors other than the one being programmed

Reduces overall programming time when issuing multiple

program command sequences

Simultaneous Read/Write Operation

—

FlexBank Architecture (PL127J/PL064J/PL032J)

CFI (Common Flash Interface) compliant

—

Erase Suspend / Erase Resume

—

Program Suspend / Program Resume

—

Unlock Bypass Program command

—

Hardware Features

Ready/Busy# pin (RY/BY#)

—

Provides a hardware method of detecting program or erase

cycle completion

Hardware method to reset the device to reading array data

At V

, hardware level protection for the first and last two 4K

word sectors.

At V

, allows removal of sector protection

At V

, provides accelerated programming in a factory setting

A command sector protection method to lock combinations of

individual sectors and sector groups to prevent program or

erase operations within that sector

Sectors can be locked and unlocked in-system at V

level

A sophisticated sector protection method to lock

combinations of individual sectors and sector groups to

prevent program or erase operations within that sector using

a user-defined 64-bit password

Standard discrete pinouts

11 x 8 mm, 80-ball Fine-pitch BGA (PL127J) (VBG080)

8.15 x 6.15 mm, 48-ball Fine pitch BGA (PL064J/PL032J)

(VBK048)

MCP-compatible pinout

8 x 11.6 mm, 64-ball Fine-pitch BGA (PL127J)

7 x 9 mm, 56-ball Fine-pitch BGA (PL064J and PL032J)

Compatible with MCP pinout, allowing easy integration of RAM

into existing designs

20 x 14 mm, 56-pin TSOP (PL127J) (TS056)

FlexBank Architecture (PL129J)

—

Hardware reset pin (RESET#)

—

WP#/ ACC (Write Protect/Acceleration) input

Persistent Sector Protection

Enhanced VersatileI/O (V

) Control

—

Password Sector Protection

Secured Silicon Sector region

—

Package options

Both top and bottom boot blocks in one device

Manufactured on 110 nm process technology

Data Retention: 20 years typical

Cycling Endurance: 1 million cycles per sector typical

—

Publication Number

S29PL-J_00

Revision

Amendment

Issue Date

July 29, 2005

This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not

design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.

A d v a n c e

I n f o r m a t i o n

General Description

The PL127J/PL129J/PL064J/PL032J is a 128/128/64/32 Mbit, 3.0 volt-only Page Mode and Si-

multaneous Read/Write Flash memory device organized as 8/8/4/2 Mwords. The devices are

offered in the following packages:

11 mm x 8 mm, 80-ball Fine-pitch BGA standalone (PL127J)

8 mm x 11.6 mm, 64-ball Fine-pitch BGA multi-chip compatible (PL127J)

8.15 mm x 6.15 mm, 48-ball Fine-pitch BGA standalone (PL064J/PL032J)

7 mm x 9 mm, 56-ball Fine-pitch BGA multi-chip compatible (PL064J and PL032J)

20 mm x 14 mm, 56-pin TSOP (PL127J)

The word-wide data (x16) appears on DQ15-DQ0. This device can be programmed in-system or

in standard EPROM programmers. A 12.0 V V

is not required for write or erase operations.

The device offers fast page access times of 20 to 30 ns, with corresponding random access times

of 55 to 70 ns, respectively, allowing high speed microprocessors to operate without wait states.

To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and

output enable (OE#) controls. Note: Device PL129J has 2 chip enable inputs (CE1#, CE2#).

Simultaneous Read/Write Operation with Zero Latency

The Simultaneous Read/Write architecture provides

simultaneous operation

by dividing the

memory space into 4 banks, which can be considered to be four separate memory arrays as far

as certain operations are concerned. The device can improve overall system performance by al-

lowing a host system to program or erase in one bank, then immediately and simultaneously

read from another bank with zero latency (with two simultaneous operations operating at any

one time). This releases the system from waiting for the completion of a program or erase op-

eration, greatly improving system performance.

The device can be organized in both top and bottom sector configurations. The banks are orga-

nized as follows:

Bank

PL127J Sectors

16 Mbit (4 Kw x 8 and 32 Kw x 31)

48 Mbit (32 Kw x 96)

16 Mbit (4 Kw x 8 and 32 Kw x 31)

PL064J Sectors

8 Mbit (4 Kw x 8 and 32 Kw x 15)

24 Mbit (32 Kw x 48)

8 Mbit (4 Kw x 8 and 32 Kw x 15)

PL032J Sectors

4 Mbit (4 Kw x 8 and 32 Kw x 7)

12 Mbit (32 Kw x 24)

4 Mbit (4 Kw x 8 and 32 Kw x 7)

CE# Control

CE1#

CE2#

PL129J Sectors

16 Mbit (4 Kw x 8 and 32 Kw x 31)

48 Mbit (32 Kw x 96)

16 Mbit (4 Kw x 8 and 32 Kw x 31)

Page Mode Features

The page size is 8 words. After initial page access is accomplished, the page mode operation pro-

vides fast read access speed of random locations within that page.

Standard Flash Memory Features

The device requires a

single 3.0 volt power supply

(2.7 V to 3.6 V) for both read and write

functions. Internally generated and regulated voltages are provided for the program and erase

operations.

The device is entirely command set compatible with the

JEDEC 42.4 single-power-supply

Flash standard.

Commands are written to the command register using standard microproces-

sor write timing. Register contents serve as inputs to an internal state-machine that controls the

S29PL-J

S29PL-J_00_A8 July 29, 2005

A d v a n c e

I n f o r m a t i o n

erase and programming circuitry. Write cycles also internally latch addresses and data needed

for the programming and erase operations. Reading data out of the device is similar to reading

from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. The Unlock Bypass

mode facilitates faster programming times by requiring only two write cycles to program data

instead of four. Device erasure occurs by executing the erase command sequence.

The host system can detect whether a program or erase operation is complete by reading the

DQ7 (Data# Polling) and DQ6 (toggle)

status bits.

After a program or erase cycle has been

completed, the device is ready to read array data or accept another command.

The sector erase architecture allows memory sectors to be erased and reprogrammed without

affecting the data contents of other sectors. The device is fully erased when shipped from the

factory.

Hardware data protection

measures include a low V

detector that automatically inhibits

write operations during power transitions. The hardware sector protection feature disables both

program and erase operations in any combination of sectors of memory. This can be achieved

in-system or via programming equipment.

The Erase Suspend/Erase Resume

feature enables the user to put erase on hold for any pe-

riod of time to read data from, or program data to, any sector that is not selected for erasure.

True background erase can thus be achieved. If a read is needed from the Secured Silicon Sector

area (One Time Program area) after an erase suspend, then the user must use the proper com-

mand sequence to enter and exit this region.

The

Program Suspend/Program Resume

feature enables the user to hold the program op-

eration to read data from any sector that is not selected for programming. If a read is needed

from the Secured Silicon Sector area, Persistent Protection area, Dynamic Protection area, or the

CFI area, after a program suspend, then the user must use the proper command sequence to

enter and exit this region.

The device offers two power-saving features. When addresses have been stable for a specified

amount of time, the device enters the

automatic sleep mode.

The system can also place the

device into the standby mode. Power consumption is greatly reduced in both these modes.

The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunnel-

ing. The data is programmed using hot electron injection.

July 29, 2005 S29PL-J_00_A8

S29PL-J