®
DEVICE
SPECIFICATION
2.5 GBPS LASER DRIVER
2.5 GBPS LASER DRIVER
GENERAL DESCRIPTION
S3049
S3049
FEATURES
•
•
•
•
•
•
•
2.5 Gbps data rate
Automatic Laser Power Control
Laser Bias Enable Input
Differential PECL Inputs
Temperature Compensated Reference Voltage
Laser Fault and Fail indicators
Selectable on-chip Re-Clocking
The S3049 has three main sections: a reference
generator, a high speed current modulation driver,
and a laser bias block with automatic power control.
The reference generator generates a temperature sta-
bilized reference voltage, V
REF
, which can be used to
program the bias and the modulation currents.
The high-speed modulation driver can switch up to
60 mA swing through the laser. The CLKSEL pin can
be used to select whether or not to re-clock the input
data.
The laser bias block sets the bias current of the laser
and has an Automatic Power Control (APC) system,
which keeps the current through the laser constant by
monitoring the current through the monitor photo-diode.
The APC loop is also used to detect excessive laser
power and low laser power. These conditions are
flagged on the LSFAULT and LSFAIL output pins
respectively.
• 60 mA Modulation Current, 90 mA Bias Current
• 32 Pin TQFP Package
APPLICATIONS
• WDM for SONET OC-48
• OC-48 Fiber optic modules
• OC-48 Line termination equipment
Figure 1. Typical Operating Circuit
VCC
VCC
VCC
VCC1
TD+
TD-
TDCLK+
TDCLK–
CLKSEL
VCC2
LSFAIL
LSFAULT
IMODMON
IBIASMON
VCC
IMOD+
PH DIODE
DISABLE
CDEL
IMOD–
IBIAS
VEE
LASER
IBCMP
IMSET
IPD
IBSET
VEE
VEE
July 27, 1999 / Revision C
IPSET
VREF
1
S3049
Figure 2. Functional Block Diagram
2.5 GBPS LASER DRIVER
+5V
TD+
TD-
DFF
+
MUX
IMOD+
CLKSEL
TDCLK+
TDCLK-
IMOD–
IBIAS
IMODMON
IBIASMON
LSFAIL
V
NOM
-V
E
+
–
Shut
Down
Control
Ref Gen
Circuit
+
V
NOM
+V
E
Vnom
LSFAULT
–
+
_
DISABLE
IPD
LASER
C
APC
IBCMP
IMSET
IBSET
IPSET
CDEL
VREF
C
DEL
2
July 27, 1999 / Revision C
PH DIODE
2.5 GBPS LASER DRIVER
DETAILED DESCRIPTION
Reference Generator
The reference generator provides temperature com-
pensated reference voltage, VREF, which is used to
program the laser diode bias current, I
BIAS
, the
modulation current, I
MOD
, and the photo-diode refer-
ence current, I
PD
. The currents are set by connecting
a resistor between VREF and the respective current
source pin.
S3049
Monitor Pins
I
BIAS
and I
MOD
are mirrored and brought out on the
IBIASMON and IMODMON pins respectively. The
monitor currents are a specified fraction of the actual
currents and are converted to a voltage by connect-
ing the pins to VCC through a resistor.
FAULT Detection
If the monitor photo-diode current increases beyond
the point which can be controlled by the APC loop,
the LSFAULT signal is asserted, indicating exces-
sive laser power (a FAULT condition). This condition
occurs when the voltage at the IPD node exceeds
V
NOM
by more than 400mv.
LSFAULT is also asserted if V
REF
is detected to ex-
ceed 3.8V, as this will generate excessively high
laser current.
Laser Bias Block with Automatic Power
Control
The laser bias current, I
BIAS
, is set by connecting a
resistor between the IBSET pin and VREF. The cur-
rent through the resistor is amplified by a gain factor,
A
IBSET
, to generate I
BIAS
.
There is a feedback configuration to adjust the laser
bias current to maintain constant laser power as la-
ser efficiency changes with temperature and age.
Light produced by the laser diode produces an aver-
age current in the monitor photo-diode. This current
flows into the IPD pin. The IPSET current source,
whose current is set by the IPSET resistor, draws
current away from the IPD node. When the two cur-
rents are equal, the voltage at that node is set by the
nominal reference voltage, V
NOM,
of a differential am-
plifier. When the currents are not equal a voltage
change is generated across the capacitor, C
APC,
which the differential amplifier translates to a voltage
which generates a current through the IBCMP resis-
tor. This current is summed with current through the
IBSET resistor which adjusts I
BIAS
until the monitor
photo-diode current equals the nominal monitor
photo-diode current, I
PD
.
FAIL Detection
If the monitor photo-diode current decreases beyond
the point which can be controlled by the APC loop,
LSFAIL is asserted, indicating low laser power (FAIL
condition). This condition occurs when the voltage at
the IPD pin drops below V
NOM
by more than 400mv.
Laser Shutdown
If a FAULT or FAIL condition is detected the laser
bias and modulation currents will be turned off.
The laser can be enabled only by toggling the DIS-
ABLE input or by initiating a power-on cycle.
LSFAULT and LSFAIL will be reset on DISABLE de-
assert or V
CC
> 4.4V.
If the CDEL pin is grounded, the shutdown of the
laser currents on a FAULT or FAIL detection is dis-
abled, and LSFAIL or LSFAULT will de-assert when
the FAULT or FAIL condition no longer exists.
Modulation Driver
The modulation driver consists of a high speed input
buffer and a differential output stage. The modula-
tion current, I
MOD
, is programmed by connecting a
resistor between the IMSET pin and VREF.
The current through the resistor is amplified by a
gain factor, A
IMSET
, to generate I
MOD
.
If the CLKSEL input is set Low, the data input, TD+/
TD–, is clocked at the input by TDCLK to provide low
jitter. If CLKSEL is High, TD+/TD– will be passed
through to the modulation driver with no re-clocking.
Start-up Sequence
The laser bias and modulation currents are turned
on within a time t
ON
from when V
CC
exceeds 4.4V or
from when the DISABLE input is de-asserted. During
the period t
DELAY
, set by the capacitor C
DEL
, the
shutdown of the laser is disabled in order to allow
the APC loop time to settle. During this time if a
FAULT or FAIL condition is detected the laser will
not be shut down as it could be caused by the APC
loop transient state. C
DEL
should be chosen such
that t
DELAY
is much longer than the APC loop settling
time. LSFAULT and LSFAIL will not assert during
t
DELAY
.
July 27, 1999 / Revision C
3
S3049
Table 1. Pin Assignment and Descriptions
Pin Name
TD+
TD-
TDCLK+
TDCLK-
CLKSEL
DISABLE
CDEL
Level
Diff.
PECL
Diff.
PECL
Diff.
PECL
Diff.
PECL
TTL
TTL
I/O
I
I
I
I
I
I
Pin #
10
12
14
16
9
17
3
Positive PECL Data Input.
Negative PECL Data Input.
Positive clock input.
Negative clock input.
2.5 GBPS LASER DRIVER
Description
A Low selects re-clocking of TD+, TD-. A High will pass the data
through without re-clocking.
High level disables bias and modulation currents. If left open it
will default to a low state.
A capacitor to ground sets the time for t
DELAY,
, the time during which
laser shutdown is disabled after Disable is de-asserted or
V
CC
> 4.4V. If this pin is grounded, laser shutdown is disabled.
A resistor to VREF sets the modulation current. (See Figure 7.)
A resistor to VREF sets the bias current. (See Figure 6.)
A resistor to VREF sets the monitor photo-diode reference current.
(See Figure 8.)
A resistor to IBSET pin sets the maximum APC loop compensation
bias current. (See Figure 9.)
Monitor photo-diode current input.
Secondary Laser Modulation Current output. When TD+ is High,
current is driven through this pin.
Primary Laser Modulation Current output. When TD+ is Low,
current is driven through this pin.
IMSET
IBSE T
IP SE T
IBCMP
IPD
IMOD-
IMOD+
Current
Current
Current
I
O
O
24
23
6
22
2
27
29
4
July 27, 1999 / Revision C
2.5 GBPS LASER DRIVER
Table 1. Pin Assignment and Descriptions (Continued)
Pin Name
IBIAS
Level
Current
I/O
O
Pin #
25
Description
Laser Bias Current output.
S3049
LSFAULT
Open
Collector
Open
Collector
Open
Collector
Open
Collector
O
8
Active High output. Asserts when excessively high laser power is
detected or V
REF
exceeds 3.8V.
Active High output. Asserts when excessively low laser power is
detected.
Modulation current monitor output. It can be used to monitor I
MOD
by connecting it to V
CC
through a resistor.
Bias current monitor output. It can be used to monitor I
BIAS
by
connecting it to V
CC
through a resistor.
Temperature compensated reference.
LSFAIL
O
7
IMODMON
O
20
IBIASMON
O
19
VREF
O
5, 21
VCC1
18
Positve supply for low frequency circuitry.
VCC2
31, 32
Positve supply for high frequency circuitry.
VEE1
4
Ground for low frequency circuitry.
VEE2
1, 28, 30
Ground for high frequency circuitry.
VEE3
26
Ground for I
BIAS
circuitry.
VEE4
11, 13, 15 Ground for high frequency input shield.
July 27, 1999 / Revision C
5
