S4242/S42WD42/S4261/S42WD61
Dual Voltage Supervisory Circuit
With Watchdog Timer(S42WD61) (S42WD42)
FEATURES
• Precision Dual Voltage Monitor
– V
CC
Supply Monitor
- Dual reset outputs for complex
microcontroller systems
- Integrated memory write lockout function
- No external components required
• Second Voltage Monitor Output
– Separate V
LOW
output
– Generates interrupt to MCU
– Generates RESET for dual supply systems
- Guaranteed output assertion to V
CC
- 1V
• Watchdog Timer (S42WD42, S42WD61)
– 1.6s
• Memory Internally Organized 2 x8
• Extended Programmable Functions
Available on SMS24
• High Reliability
– Endurance: 100,000 erase/write cycles
– Data retention: 100 years
OVERVIEW
The S42xxx are a precision power supervisory circuit. It
automatically monitors the device’s V
CC
level and will
generate a reset output on two complementary open drain
outputs. In addition to the V
CC
monitoring, the S42xxx also
provides a second voltage comparator input. This input
has an independent open drain output that can be wire-
OR’ed with the RESET I/O or it can be used as a system
interrupt.
The S42xxx also has an integrated 4k/16k-bit nonvolatile
memory. The memory conforms to the industry standard
two-wire serial interface. In addition to the reset circuitry,
the S42WD42/S42WD61 also has a watchdog timer.
BLOCK DIAGRAM
VCC
8
SCL
SDA
6
5
NONVOLATILE
MEMORY
ARRAY
WRITE
CONTROL
PROGRAMMABLE
RESET PULSE
GENERATOR
2
RESET#
+
–
VTRIP
RESET
CONTROL
7
PROGRAMMABLE
WATCHDOG
TIMER
(S42WD42,
S42WD61)
1
UV
VSENSE
3
+
–
OV
1.26V
4
GND
2025 T BD 2.0
RESET
VLOW#
SUMMIT MICROELECTRONICS, Inc.
•
300 Orchard City Drive, Suite 131
•
Campbell, CA 95008
•
Telephone 408-378-6461
•
Fax 408-378-6586
•
www.summitmicro.com
© SUMMIT MICROELECTRONICS, Inc. 2000
2025 6.0 4/17/00
Characteristics subject to change without notice
1
S4242/S42WD42/S4261/S42WD61
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias
............................................................................................................................... -40°C to +85°C
Storage Temperature
..................................................................................................................................... -65°C to +125°C
Soldering Temperature (less than 10 seconds) ................................................................................................................... 300°C
Supply Voltage ............................................................................................................................................................. 0 to 6.5V
Voltage on Any Pin ....................................................................................................................................... -0.3V to V
CC
+0.3V
ESD Voltage (JEDEC method) .......................................................................................................................................... 2,000V
NOTE: These are STRESS ratings only. Appropriate conditions for operating these devices are given elsewhere in this specification. Stresses
beyond those listed here may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min
0°C
-40°C
Max
+70°C
+85°C
2025 PGM T1.0
DC ELECTRICAL CHARACTERISTICS
(over recommended operating conditions unless otherwise specified)
Symbol
I
CC
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL
Parameter
Supply Current (CMOS)
Standby Current (CMOS)
Input Leakage
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Conditions
SCL = CMOS Levels @ 100KHz
SDA = Open
All other inputs = GND or V
CC
SCL = SDA = V
CC
All other inputs = GND
V
IN
= 0 To V
CC
V
OUT
= 0 To V
CC
SCL, SDA, RESET# (pin 2)
SCL, SDA, RESET (pin7)
I
OL
= 3mA SDA
V
CC
=5.5V
V
CC
=3.3V
V
CC
=5.5V
V
CC
=3.3V
Min
Max
3
2
50
25
10
10
0.3xV
CC
0.7xV
CC
0.4
Units
mA
mA
µA
µA
µA
µA
V
V
V
2025 PGM T2.0
AC ELECTRICAL CHARACTERISTICS
(over recommended operating conditions unless otherwise specified)
Symbol
Parameter
SCL Clock Frequency
Clock Low Period
Clock High Period
Bus Free Time
Start Condition Setup Time
Start Condition Hold Time
Stop Condition Setup Time
Clock to Output
Data Out Hold Time
SCL and SDA Rise Time
SCL and SDA Fall Time
Data In Setup Time
Data In Hold Time
Noise Spike Width
@ SCL, SDA Inputs
Write Cycle Time
Noise Suppression Time Constant
SCL Low to SDA Data Out Valid
SCL Low to SDA Data Out Change
Before New Transmission
Conditions
2.7V to 4.5V
Min
0
4.7
4.0
4.7
4.7
4.0
4.7
0.3
0.3
1000
300
250
0
100
10
3.5
Max
100
4.5V to 5.5V
Min
Max
400
1.3
0.6
1.3
0.6
0.6
0.6
0.2
0.2
300
300
100
0
100
10
0.9
Units
KHz
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ms
2025 PGM T3.0
f
SCL
t
LOW
t
HIGH
t
BUF
t
SU:STA
t
HD:STA
t
SU:STO
t
AA
t
DH
t
R
t
F
t
SU:DAT
t
HD:DAT
T
I
t
WR
2025 6.0 4/17/00
2
S4242/S42WD42/S4261/S42WD61
CAPACITANCE
T
A
= 25°C, f = 100KHz
Symbol
CIN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Max
5
8
Units
pF
pF
2025 PGM T4.0
tR
tF
tHIGH
tLOW
SCL
tSU:SDA
tHD:DAT
tSU:DAT
tSU:STO
tHD:SDA
tBUF
SDA In
tAA
tDH
SDA Out
2025 Fig01 1.0
FIGURE 1. BUS TIMING
START
Condition
SCL
STOP
Condition
SDA In
2025 Fig02 1.0
FIGURE 2. START AND STOP CONDITIONS
2025 6.0 4/17/00
3
S4242/S42WD42/S4261/S42WD61
tGLITCH
VCC
VTRIP
VRVALID
tPURST
tRPD
tPURST
RESET#
tRPD
RESET
FIGURE 3. RESET OUTPUT TIMING
2025 T fig03 2.0
RESET CIRCUIT AC and DC ELECTRICAL CHARACTERISTICS
TA=-40°C to +85°C
Symbol
V
TRIP
Parameter
Reset Trip Point
Part no.
Suffix
A (or) Blank
B
2.7
Min.
4.250
4.50
2.7
Typ.
4.375
4.625
2.9
200
Max.
4.5
4.75
3.10
5
1
30
0.4
V
CC
-.75
1.20
1.20
1.20
1.20
1.25
1.25
1.25
1.25
1.30
1.30
1.30
1.30
5
5
1600
Unit
V
V
V
ms
µs
V
ns
V
V
V
V
V
V
µs
µs
ms
2025 PGM T5.2
t
PURST
t
RPD
V
RVALID
t
GLITCH
V
OLRS
V
OHRS
V
ULH
V
UHL
V
OLH
V
OHL
t
VD1
t
VD2
t
WDTO
Reset Timeout
V
TRIP
to RESET Output Delay
RESET Output Valid to V
CC
min. Guarantee
Glitch Reject Pulse Width note 1
RESET Output Low Voltage I
OL
= 1mA
RESET High Voltage Output I
OH
= 800µA
V
SENSE
Under-voltage threshold low to high
V
SENSE
Under-voltage threshold high to low
V
SENSE
Over-voltage threshold low to high
V
SENSE
Over-voltage threshold high to low
Delay to V
LOW
Active
Delay to V
LOW
Released
Watchdog timeout Period (S42WD61)
(S42WD42)
2025 6.0 4/17/00
4
S4242/S42WD42/S4261/S42WD61
V
ULH
V
SENSE
(Under-voltage detect)
V
UHL
t
VD1
t
VD2
V
LOW
#
2025 T fig04 2.0
FIGURE 4. V
SENSE
UNDER-VOLTAGE FUNCTION
RESET# (in)
RESET# (out)
t
PURST
t
PURST
RESET (out)
2025 T fig05 2.0
FIGURE 5. RESET AS AN INPUT
2025 6.0 4/17/00
5
