S6C1108
6 BIT 384 CHANNEL RSDS TFT-LCD SOURCE DRIVER
Nov. 2002.
Ver. 0.2
S6C1108
6 BIT 384 CHANNEL RSDS SOURCE DRIVER
INTRODUCTION
The S6C1108 is a Source Driver suitable for Reduced Swing Differential Signaling(RSDS) digital interface.
It converts 18-bit digital data into the analog voltage for 384 channels, charging each sub-pixel to the correct gray
level corresponding to the digital value.
The RSDS path to the panel timing controller contributes toward lowering radiated EMI, reducing system power
consumption and eliminates one of the two pixel busses used in typical XGA, SXGA TFT LCD panels.
This single 9-bit differential bus conveys the 18-bit color data for XGA, SXGA panels.
FEATURES
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TFT active matrix LCD source driver LSI
64G/S is possible through 14(7 by 2) external power supply and D/A converter
Both dot inversion display and N-line inversion display are possible
Compatible with gamma-correction
Charge sharing function
Logic supply voltage[VDD1] : 2.7 to 3.6 V
LCD driver supply voltage[VDD2] : 7.0 to 12.0 V
Output dynamic range: VSS2+0.2V to VDD2-0.2V
Maximum operating frequency: fmax=85 MHz (internal data transmission rate at 2.7 V operation)
Output: 384 outputs
Reduced Swing Differential Signaling(RSDS) interface for low power consumption and low EMI.
Minimum RSDS input swing level(CLKP, CLKN, DATAP, DATAN): 100mV
Data bus interface control pin (DATPOL)
TCP or COF supported
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6 BIT 384 CHANNEL RSDS SOURCE DRIVER
S6C1108
BLOCK DIAGRAM
Y382
Y383
6
Y384
6
Y1
POL
Y2
Y3
Output Buffer
VGMA1 to VGMA14
14
R-DAC
6
6
6
6
CLK1
Data Latches
6
D00P
D00N
D01P
D01N
D22P
D22N
DATPOL
CLKP
CLKN
RSDS Receiver
Data Register
6
6
6
6
6
128 bit Shift Register
DIO1
SHL
DIO2
Figure 1. S6C1108 Block Diagram
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S6C1108
6 BIT 384 CHANNEL RSDS SOURCE DRIVER
PIN ASSIGNMENTS
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
TESTI1
TESTO1
DIO1
D00N
D00P
D01N
D01P
D02N
D02P
DATPOL
POL
CLK1
CLKN
CLKP
VSS1
VGMA1
VGMA2
VGMA3
VGMA4
VGMA5
VGMA6
VGMA7
VSS2
VDD2
VGMA8
VGMA9
VGMA10
VGMA11
VGMA12
VGMA13
VGMA14
SHL
VDD1
D10N
D10P
D11N
D11P
D12N
D12P
D20N
D20P
D21N
D21P
D22N
D22P
DIO2
TESTO2
TESTI2
Y372
Y373
Y374
Y375
Y376
Y377
Y378
Y379
Y380
Y381
Y382
Y383
Y384
Output 384
S6C1108
Input 48
Figure 2. S6C1108 Pin Assignments
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6 BIT 384 CHANNEL RSDS SOURCE DRIVER
S6C1108
PIN DESCRIPTIONS
Symbol
VDD1
VDD2
VSS1
VSS2
Y1 to Y384
D0P<0:2>
D0N<0:2>
D1P<0:2>
D1N<0:2>
D2P<0:2>
D2N<0:2>
SHL
DIO1
DIO2
DATPOL
Pin Name
Logic power supply
Driver power supply
Logic ground
Driver ground
Driver outputs
2.7 to 3.6 V
7.0 to 12.0 V
Ground (0 V)
Ground (0 V)
The D/A converted 64 gray-scale analog voltage is output.
Total data lines consist of 18 data bus.
(6-bit digital, 3 colors(R, G, B) and 2 differential input pairs)
The 3-bit differential input pairs generate the internal 6-bit data through
the comparison between DxxP and DxxN.
This pin controls the direction of shift register in cascade connection.
When SHL=H: DIO1 input, Y1→Y384, DIO2 output
When SHL=L: DIO2 input, Y384→Y1, DIO1 output
SHL=H: Used as the start pulse input pin.
SHL=L: Used as the start pulse output pin.
SHL=H: Used as the start pulse output pin.
SHL=L: Used as the start pulse input pin.
DATPOL= L: No inversion
DATPOL= H: Data polarity inversion
( DATPOL must be fixed VSS1 or VDD1.)
POL=H: The reference voltage for odd number outputs are VGMA1 to
VGMA7 and those for even number outputs are VGMA8 to VGMA14.
POL=L: The reference voltage for odd number outputs are VGMA8 to
VGMA14 and those for even number outputs are VGMA1 to VGMA7.
The RSDS clock input pairs generate the internal shift clock, CLK2,
through the comparison between CLKP and CLKN.
S6C1108 clears 128 shift registers at the rising edge of CLK1 and
outputs the analog data to the each channel at the falling edge.
Description
RSDS data input
Shift direction control
input
Start pulse input/output
Start pulse input/output
Data inversion input
POL
CLKP
CLKN
CLK1
VGMA1
to VGMA14
TESTI1/O1,
TESTI2/O2
Polarity input
RSDS shift clock input
Latch input
Input the gamma corrected power supplies from external source.
Gamma corrected power
VDD2>VGMA1>VGMA2>……>VGMA13>VGMA14>VSS2
supplies
Keep power supplies unchanged during the gray-scale voltage output.
Amp test input/output
These pins are used for Amp test.
TESTI1(=TESTI2)=L : Normal operation mode
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